| Texto completo | |
| Autor(es): |
Ribeiro, Thales Augusto
[1]
;
Bergamaschi, Flavio Enrico
[1]
;
Barraud, Sylvain
[2, 3]
;
Pavanello, Marcelo Antonio
[1]
Número total de Autores: 4
|
| Afiliação do(s) autor(es): | [1] Ctr Univ FEI, Dept Elect Engn, Sao Bernardo Do Campo - Brazil
[2] Univ Grenoble Alpes, Grenoble - France
[3] LCTE CEA, SCME, MINATEC Campus, Dept Composants Silicium, LETI, Grenoble - France
Número total de Afiliações: 3
|
| Tipo de documento: | Artigo Científico |
| Fonte: | Solid-State Electronics; v. 185, NOV 2021. |
| Citações Web of Science: | 1 |
| Resumo | |
This work studied the effects of the fin width variation on Silicon-on-Insulator Junctionless Nanowire Transistors (JNTs) working in the temperature range of 300 K to 500 K. The effects of the temperature on the measured drain current and gate capacitance, and on the extracted electrical parameters such as the threshold voltage, the subthreshold slope, and the electron mobility were analyzed. Results show that JNTs with larger fin width may present better carrier mobility at a higher temperature than narrow ones as the degradation due to phonon scattering is decreased and the impurity scattering becomes more relevant. It is demonstrated that JNTs with narrow fin width show higher phonon scattering and higher mobility variation with the temperature than wider ones. (AU) | |
| Processo FAPESP: | 16/10832-1 - Avaliação e modelagem do transporte de carga em transistores mos nanométricos para projeto de circuitos cmos |
| Beneficiário: | Thales Augusto Ribeiro |
| Modalidade de apoio: | Bolsas no Brasil - Doutorado |
| Processo FAPESP: | 19/15500-5 - Simulação atomística das propriedades elétricas de nanofios transistores MOS |
| Beneficiário: | Marcelo Antonio Pavanello |
| Modalidade de apoio: | Auxílio à Pesquisa - Regular |