Accounting for Series Resistance in the Compact Model of Triple-Gate Junctionless Nanowire Transistors

Autor(es)

Trevisoli, Renan ; Doria, Rodrigo T. ; de Souza, Michelly ; Pavanello, Marcelo A. ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO); v. N/A, p. 4-pg., 2018-01-01.

Resumo

The aim of this work is to propose a method to account for the series resistance effect on the compact drain current model of Junctionless Nanowire Transistors. The model is validated through comparisons against iterative analysis and three-dimensional numerical simulations. The characteristics of the devices, i.e. the width, height, channel length, doping concentration and gate oxide thickness, have been varied in the analysis to demonstrate the model applicability. (AU)

• Processo FAPESP: 14/18041-8 - Caracterização elétrica e modelagem de dispositivos eletrônicos avançados
• Beneficiário: Renan Trevisoli Doria
• Modalidade de apoio: Bolsas no Brasil - Pós-Doutorado