| Autor(es): |
Costa, Fernando J.
;
Pavanello, Marcelo A.
;
Trevisoli, Renan
;
Doria, Rodrigo T.
;
IEEE
Número total de Autores: 5
|
| Tipo de documento: | Artigo Científico |
| Fonte: | 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS; v. N/A, p. 4-pg., 2017-01-01. |
| Resumo | |
This work presents an analysis of the thermal resistance of Ultra-Thin Body and Buried Oxide (UTBB) SOI (Silicon-on-Insulator) MOSFETs (Metal Oxide Semiconductor Field Effect Transistor) under a selected set of back gate biases (V-sub), with and without considering the effect of the ground plane. It has been shown that the thermal resistance increases as the substrate bias is reduced. For negative V-sub, a thicker depletion depth is induced by the back gate, confining the overall current closer to the front gate and increasing its density. A thermal resistance reduction of about 8-9% can be obtained by simply increasing the back bias from -2V up to 2 V. (AU) | |
| Processo FAPESP: | 14/18041-8 - Caracterização elétrica e modelagem de dispositivos eletrônicos avançados |
| Beneficiário: | Renan Trevisoli Doria |
| Modalidade de apoio: | Bolsas no Brasil - Pós-Doutorado |