Scaling Up Loop Pipelining For High-Level Synthesis: A Non-Iterative Approach

Autor(es)

Rosa, Leandro de Souza ; Bonato, Vanderlei ; Bouganis, Christos-Savvas ; IEEE

• Tipo de documento: Artigo Científico
• Fonte: 2018 INTERNATIONAL CONFERENCE ON FIELD-PROGRAMMABLE TECHNOLOGY (FPT 2018); v. N/A, p. 8-pg., 2018-01-01.

Resumo

High-level synthesis is a powerful tool for increasing productivity in digital hardware design. However, as digital systems become larger and more complex, designers have to consider an increased number of optimizations and directives offered by highlevel synthesis tools to control the hardware generation process, resulting in a large design space to be explored. One of the most impactful optimizations is loop pipelining due to its large improvement in the hardware throughput. Nevertheless, the modulo scheduling algorithms that are used for loop pipelining are computationally expensive, and their application to the whole design space can make its exploration inviable, leading to sub-optimum solutions. Current state-of-the-art tools for modulo scheduling follow an iterative approach, which solves O(n(2)) optimization problems, where n is the loop code size. To address this problem, this work proposes a novel data-flow-based approach that solves exactly 2 optimization problems, independently of the loop code size. Results show orders-of-magnitude savings in the computation time, leading to significant design space exploration time savings when compared with the state-of-the-art. As such, the proposed method produces hardware designs of higher performance than the ones produced by the current state of the art for large and complex loops, maintaining a similar resource utilization. (AU)

• Processo FAPESP: 14/14918-2 - Identificação de trechos de código para processamento pipeline em aceleradores FPGA para plataformas heterogêneas
• Beneficiário: Leandro de Souza Rosa
• Modalidade de apoio: Bolsas no Brasil - Doutorado Direto