Execution of algorithms using dynamic data flow model for reconfigurable hardware: accelerating object identification software

• Grant number: 06/05664-0
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: January 01, 2007
• End date: December 31, 2007
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Jorge Luiz e Silva
• Grantee: Luiz Carlos Lucca
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil

Abstract

The (DDFG) Dynamic Dataflow Model plus a partial reconfigurable hardware is a project to explore the parallelism in many applications, yielding a greater relation for the nature of the dataflow process and the partial reconfigurable model. This project has provided a proof-of-concepts for different parts of the system. Specifically, on this project, we intend to generate a proof-of-concept for the protocol Tagged-token into the EDK system from Xilinx Spartan-3.