| Full text | |
| Author(s): |
Jordan, Michael Guilherme
;
Korol, Guilherme
;
Knorst, Tiago
;
Rutzig, Mateus Beck
;
Schneider Beck, Antonio Carlos
;
Kastensmidt, F
;
Reis, R
;
Todri-Sanial, A
;
Li, H
;
Metzler, C
Total Authors: 10
|
| Document type: | Journal article |
| Source: | 2023 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, ISVLSI; v. N/A, p. 6-pg., 2023-01-01. |
| Abstract | |
Cloud warehouses have been adopting CPU-FPGA environments to accelerate clients' applications with scalability. On the CPU side, DVFS improves energy efficiency. On the FPGA side, High-Level Synthesis enables hardware optimizations that lead to designs with variant characteristics (e.g., latency and power). Although both techniques have been used, they have never been cooperatively exploited to improve execution efficiency. For that, we propose RAHD, a framework that bridges the gap between DVFS, HLS multiple design versions, and CPU-FPGA environments. RAHD offers automatic fine-tuning selection of design versions and DVFS to efficiently balance workload, achieving 32.86x energy improvements over a standard provisioning strategy. (AU) | |
| FAPESP's process: | 21/06825-8 - ADAPTT: providing resource efficiency in traffic classification through the synergistic and adaptive use of FPGAs and CNNs |
| Grantee: | Antonio Carlos Schneider Beck Filho |
| Support Opportunities: | Regular Research Grants |