| Full text | |
| Author(s): |
Brito, Patrick H. S.
;
de Lemos, Rogerio
;
Rubira, Cecilia M. F.
;
IEEE
Total Authors: 4
|
| Document type: | Journal article |
| Source: | 2009 JOINT WORKING IEEE/IFIP CONFERENCE ON SOFTWARE ARCHITECTURE AND EUROPEAN CONFERENCE ON SOFTWARE ARCHITECTURE; v. N/A, p. 2-pg., 2009-01-01. |
| Abstract | |
This paper considers the representation of different software fault tolerance techniques as a product line architecture (PLA) for promoting the muse of software artifact. The proposed PLA enables to specify a series of closely related architectural applications, which is obtained by identifying variation points associated with design decisions regarding software fault tolerance. These decisions are used to choose the appropriate technique depending on the features selected, e.g, the number of redundant resources, or the type of adjudicator. The proposed approach also comprises the formalisation of the PLA, using B-Method and CSP, for systematising the verification of fault-tolerant software systems at the architectural level. The properties verified cover two complementary contexts: the selection of the correct architectural variabilities for instantiating the PLA, and also the properties of the chosen fault tolerance techniques. (AU) | |