Analysis of SRAM-Based FPGA SEU Sensitivity to Combined EMI and TID-Imprinted Effects

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Benfica, Juliano ; Green, Bruno ; Porcher, Bruno C. ; Poehls, Leticia Bolzani ; Vargas, Fabian ; Medina, Nilberto H. ; Added, Nemitala ; de Aguiar, Vitor A. P. ; Macchione, Eduardo L. A. ; Aguirre, Fernando ; Silveira, Marcilei A. G. ; Perez, Martin ; Sofo Haro, Miguel ; Sidelnik, Ivan ; Blostein, Jeronimo ; Lipovetzky, Jose ; Bezerra, Eduardo A.

• Document type: Journal article
• Source: IEEE Transactions on Nuclear Science; v. 63, n. 2, p. 7-pg., 2016-04-01.

Abstract

This work proposes a novel methodology to evaluate SRAM-based FPGA's susceptibility with respect to Single-Event Upset (SEU) as a function of noise on VDD power pins, Total-Ionizing Dose (TID) and TID-imprinted effect on BlockRAM cells. The proposed procedure is demonstrated for SEU measurements on a Xilinx Spartan 3E FPGA operating in an 8 MV Pelletron accelerator for the SEU test with heavy-ions, whereas TID was deposited by means of a Shimadzu XRD-7000 X-ray diffractometer. In order to observe the TID-induced imprint effect inside the BlockRAM cells, a second SEU test with neutrons was performed with Americium/Beryllium ((AmBe)-Am-241). The noise was injected into the power supply bus according to the IEC 61.000-4-29 standard and consisted of voltage dips with 16.67% and 25% of the FPGA's VDD at frequencies of 10 Hz and 5 kHz, respectively. At the end of the experiment, the combined SEU failure rate, given in error/bit. day, is calculated for the FPGA's BlockRAM cells. The combined failure rate is defined as the average SEU failure rate computed before and after exposition of the FPGA to the TID. (AU)

• FAPESP's process: 12/03383-5 - Development of methodology for radiation tests on electronic components
• Grantee: Nilberto Heder Medina
• Support Opportunities: Regular Research Grants