| Author(s): |
Moreira, Luiz Carlos
;
Fontebasso Neto, Jose
;
Ferauche, Thiago
;
Silva Novaes, Guilherme Apolinario
;
Torres Rios, Emmanuel
;
IEEE
Total Authors: 6
|
| Document type: | Journal article |
| Source: | 2017 IEEE 8TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS); v. N/A, p. 4-pg., 2017-01-01. |
| Abstract | |
a new circuit technique, the reconfigurable pulse generator circuit is proposed to produce a pulse width inversely proportional to the spectrum power bandwidth in the Impulse Radio Ultra-Wide Band (IR-UWB) circuits. The complete circuit was based on two pulse generator blocks using Positive Pulse Generator (PPG), and Negative Pulse Generator (NPG) to compose a rectangular waveform at the output. These pulse generators have been implemented with high impedance circuits and are selected by digital control signals. Thus, each block can be adjusted to generate up to eight sequential pulses per clock edge. The circuit was designed to use Binary Phase Shift Keying (BPSK) scheme for modulation and can change the frequency spectrum of the signal pulses. In addition, we implemented a voltage divider circuit using two transistors in parallel with a charge pump circuit to control the signal amplitude at the output. The proposed pulse generator circuit operates at a maximum operation frequency at 12 GHz. The pos-layout simulations were performed using LTSpice, and the results show a pulse amplitude of 160mV and an average power consumption of 11.3 fJ per pulse at lowest operating frequency and 85.3 fJ per pulse at highest operating frequency, for a Pulse Repetition Frequency (PRF) of 100MHz at 1.3V power supply voltage. The core chip size occupies a very small area of 210 mu m x 75 mu m (without PAD` s). (AU) | |
| FAPESP's process: | 16/15857-2 - Reconfigurable IR-UWB transmitter design using PRC pulse in 130nm process CMOS technology |
| Grantee: | Luiz Carlos Moreira |
| Support Opportunities: | Regular Research Grants |