Loragithmic pixel CMOS with extended swing range output

• Grant number: 12/14343-4
• Support Opportunities: Regular Research Grants
• Start date: July 01, 2014
• End date: December 31, 2015
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits
• Principal Investigator: Fernando de Souza Campos
• Grantee: Fernando de Souza Campos
• Host Institution: Faculdade de Engenharia (FE). Universidade Estadual Paulista (UNESP). Campus de Bauru. Bauru , SP, Brazil

Abstract

This research project aims at developing a new architecture of CMOS pixels to present outing logarithm of the voltage signal output extended. The pixel architecture proposed in this project is to achieve the increased excursion of the voltage signal output by increasing the number of transistors connected in series as a diode. This architecture differs from conventional architecture of the pixels only in the number of transistors connected in series such as diode and therefore does not result in increased consumption and complexity of the pixel. It is intended to manufacture the devices in the technology of 0.35um Austriamicrosystems. Different pixels of tests with different number of transistors in series will be analyzed, measured and compared. It should be noted the effect of increasing the number of transistors connected as diode signal excursion of output voltage, the fill factor, the temporal noise in the amount of dark and the overall quantum efficiency (AU)