Speculative code execution for multicore architectures

• Grant number: 15/04285-5
• Support Opportunities: Scholarships in Brazil - Doctorate (Direct)
• Start date: June 01, 2015
• End date: December 31, 2016
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Guido Costa Souza de Araújo
• Grantee: Juan Jesús Salamanca Guillén
• Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil
• Associated scholarship(s): 15/12077-3 - Speculative code execution for multicore architectures, BE.EP.DD

Abstract

This proposal describes a novel software-controlled speculation technique for the parallel execution of multiple alternative traces of hot code regions. This technique, called Speculative Trace Execution (STE), enumerates, optimizes, and speculatively executes traces of hot regions such as loops and functions. It requires hardware support that can be provided in a similar fashion as that available in Hardware Transactional Memory (HTM) systems. This project discusses the necessary features to support software-controlled trace speculation, namely multi-versioning, lazy conflict detection and transaction synchronization. A comparison of existing HTM architectures - Intel TSX, IBM BG/Q, and IBM POWER8 - shows that none of them have all the features required to implement STE. As a demonstration and proof of concept, we use privatization and pause/resume code to create a prototype STE implementation. Using this prototype, Intel TSX and benchmarks from Parboil, MediaBench, and SPEC2006, we found that STE results in whole-program speedups of the order of 5%. This initial result is promising given that the prototype has significant overhead caused by the code that compensates for TSX absent features. An analysis, included in this proposal, suggests that HTM mechanisms have the potential to considerably improve trace performance provided they efficiently implement the suggested features. This preliminary work was submitted for publication to the SPAA 2015: 27th ACM Symposium on Parallelism in Algorithms and Architectures. In order to conclude this project, we are going to integrate the prototype into a real compiler and evaluate its implementation. In addition, we are going to design a HTM system simulator, amenable for trace execution, so as to study and evaluate the possible best speedups one can achieve from STE on HTM. Finally, we are going to report the results and write the thesis. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

SALAMANCA, JUAN; AMARAL, JOSE NELSON; ARAUJO, GUIDO; RIVERA, FF; PENA, TF; CABALEIRO, JC. Performance Evaluation of Thread-Level Speculation in Off-the-Shelf Hardware Transactional Memories. EURO-PAR 2017: PARALLEL PROCESSING, v. 10417, p. 15-pg., 2017-01-01. (13/08293-7, 15/04285-5, 15/12077-3)

MATTOS, LUIS; CESAR, DIVINO; SALAMANCA, JUAN; DE CARVALHO, JOAO P. L.; PEREIRA, MARCIO; ARAUJO, GUIDO; IEEE. DOACROSS Parallelization based on Component Annotation and Loop-carried Probability. 2018 30TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD 2018), v. N/A, p. 4-pg., 2018-01-01. (13/08293-7, 16/15337-9, 15/04285-5)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

GUILLÉN, Juan Jesús Salamanca. Especulação de threads usando arquiteturas de memória transacional em hardware. 2016. Doctoral Thesis - Universidade Estadual de Campinas (UNICAMP). Instituto de Computação Campinas, SP.