| Grant number: | 15/12077-3 |
| Support Opportunities: | Scholarships abroad - Research Internship - Doctorate (Direct) |
| Start date: | September 07, 2015 |
| End date: | July 06, 2016 |
| Field of knowledge: | Physical Sciences and Mathematics - Computer Science - Computer Systems |
| Principal Investigator: | Guido Costa Souza de Araújo |
| Grantee: | Juan Jesús Salamanca Guillén |
| Supervisor: | José Nelson Amaral |
| Host Institution: | Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil |
| Institution abroad: | University of Alberta, Canada |
| Associated to the scholarship: | 15/04285-5 - Speculative code execution for multicore architectures, BP.DD |
Abstract This proposal describes a novel software-controlled speculation technique for the optimization and simultaneous execution of multiple alternative traces of hot code regions. This technique, called Speculative Trace Optimization (STO), enumerates, optimizes, and speculatively executes traces of hot loops. It requires hardware support that can be provided in a similar fashion as that available in Hardware Transactional Memory (HTM) systems. This project discusses the necessary features to support software-controlled trace speculation, namely multi-versioning, lazy conflict resolution, eager conflict detection, and transaction synchronization. A review of existing HTM architectures - Intel TSX, IBM BG/Q, and IBM POWER8 - shows that none of them have all the features required to implement STO. However, this work demonstrates that STO can be implemented on top of existing HTM architectures through the addition of privatization and pause/resume code. The evaluation of a prototype STO implementation, on top of Intel TSX, using benchmarks from Parboil, MediaBench, and SPEC2006, indicates that STO results in whole-program speedups up to 9%. This initial result is promising given that the prototype has significant overhead caused by the code that compensates for TSX absent features. An analysis, included in this proposal, suggests that HTM mechanisms have the potential to considerably improve trace performance provided they efficiently implement the suggested features. In order to conclude this project, we are studying and implementing another approach on Thread-Level Speculation in iterations. Also, we are going to implement STO on another HTM System as Power8. In addition, we are going to design a HTM system simulator, amenable for trace execution, so as to study and evaluate the possible best speedups one can achieve from STO on HTM. Finally, we are going to report the results and write the thesis. (AU) | |
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