Intelligent system for automatic generation of digital circuits in FPGA using the simulated annealing algorithm

• Grant number: 16/20303-6
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: January 01, 2017
• End date: December 31, 2017
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computing Methodologies and Techniques
• Principal Investigator: Emerson Carlos Pedrino
• Grantee: Bruno Rodrigues Aguilar Figueiredo
• Host Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos , SP, Brazil

Abstract

In this research project, it is intended to implement a flexible and dedicated system for the generation of digital circuits (combinational and sequential) in an automatic fashion directly into a FPGA. The development will be performed internally to the device in order to obtain resolutions to practical problems, thereby decreasing the system training time when compared to other approaches in the literature. Thus, by means of the Simulated Annealing algorithm, a single solution will be used instead of a population of solutions in order to facilitate the implementation in hardware of the system. Therefore, the contribution of this project will be to develop a tool able to generate logic circuits using logic gates, such as AND, OR and NOT, along with sequential blocks (Flip-flops), so that to generate a fast and accurate solution, with lower power consumption, logic blocks and memory. Therefore, this project could be used in a complementary way, as circuit design alternative technique in introductory courses in digital circuits, and as support in practical projects developed by professionals in the field of digital systems and computer architecture. (AU)