Automatic Parameter Detection in RISC-V Processors

• Grant number: 25/14676-3
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: December 01, 2025
• Status: Discontinued
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Rodolfo Jardim de Azevedo
• Grantee: Gabriel Cabral Romero Oliveira
• Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil
• Associated scholarship(s): 26/11305-7 - Advanced Architectural Inference for RISC-V Verification: A Hybrid Compiler and Machine Learning Approach, BE.EP.IC

Abstract

Modern computing systems - ranging from low-power embedded devices to high-performance platforms used in servers, data centers, and scientific applications - incorporate a wide variety of processors. This heterogeneity is being further driven by the recent rise of open architectures, such as RISC-V, which offer greater flexibility of use and are free from instruction set royalties. In this context, numerous open-source implementations of RISC-V processors have emerged, making it increasingly difficult for system designers to choose the most appropriate processors. At the Computer Systems Laboratory of the Institute of Computing, the ProcessorCI project was developed to provide continuous integration for the verification of RISC-V processors, and it currently includes over 80 open-source implementations. Within this scope, it is necessary to identify specific parameters for each processor, such as the description language, word size, cache presence and size, pipeline structure, and implemented extensions. The main goal of this project is to develop an automated, generic, and non-intrusive solution to detect features of processors based on the RISC-V architecture, thus facilitating their integration into ProcessorCI. As outcomes, detection scripts will be developed, and the project will also explore the use of large language models (LLMs) as a supporting tool for characterization. Key challenges of the project include: (1) Learning a variety of hardware description languages and how to interpret them; (2) Understanding computer architecture concepts and how to detect them in source code; and (3) Learning and applying LLMs to address more complex detection tasks. (AU)