Image reconstruction through electrical impedance tomography using massively parallelized simulated annealing.

Author(s)

Renato Seiji Tavares

• Document type: Doctoral Thesis
• Press: São Paulo.
• Institution: Universidade de São Paulo (USP). Escola Politécnica (EP/BC)
• Defense date: 2016-05-06

Examining board members

Marcos de Sales Guerra Tsuzuki; Marco Aurélio Amaral Henriques; Raúl González Lima; Olavo Luppi Silva

• Advisor: Marcos de Sales Guerra Tsuzuki; Thiago de Castro Martins

Abstract

Electrical impedance tomography is a new medical imaging modality with remarkable advatanges over other stablished modalities. Simulated annealing is an algorithm that renders quality solutions despite the use of simple regularization methods and the absence of a priori information. However, it remains the need to reduce its processing time. This work takes a step in this direction, presenting a method for the reconstruction of EIT images using simulated annealing and GPU parallelization. The parallelization of matrix operations in GPU is explained, with a thread scheduling strategy that allows the effective parallelization of not-yet effectively parallelized algorithms. There are strategies for improving its performance, such as the presented outside-in heuristic. It is proposed a new sparse matrix representation focused on the CUDA architecture characteristics, with improved global memory access patterns and thread efficiency. This new matrix representation showed several advantages over the most common formats. The massive parallelization of the TIE\'s inverse problem using simulated annealing is studied, with a proposed hybrid approach that uses parallelization in both CPU and GPU. Results showed that the performance gain for the inverse problem is higher than the one obtained for the forward problem. The GPU device saturates with meshes of size of approximately 7,000 nodes, with a performance gain around 5 times faster than serial implementations. GPU parallelization may be used for the reconstruction of electrical impedance tomography images. (AU)

• FAPESP's process: 10/18658-4 - Simulated Annealing Applied to Electrical Impedance Tomography Image Reconstruction
• Grantee: Renato Seiji Tavares
• Support Opportunities: Scholarships in Brazil - Doctorate