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| Author(s): |
João Paulo Labegalini de Carvalho
Total Authors: 1
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| Document type: | Master's Dissertation |
| Press: | Rio Claro. 2016-06-22. |
| Institution: | Universidade Estadual Paulista (Unesp). Instituto de Geociências e Ciências Exatas. Rio Claro |
| Defense date: | 2016-06-07 |
| Advisor: | Alexandro José Baldassin |
| Abstract | |
The limited performance gain due to micro-architectural optimizations and the modest increase in clock rate led the microprocessor industry to seek alternatives to single-core processors in order to keep up with the performance demand. The solution found was to build architectures with multiple execution flows (multicore). Nonetheless, the parallel model’s immediate adoption requires programmers to explicitly code applications in a way that all cores are used. Yet this task has proven to be non-trivial and prone to errors, which are generally hard to detect. A new concurrent programming model known as transactional memory (TM) brings abstractions that ease the synchronization burdens of parallel coding and enables programmers to better exploit the parallelism of multicore architectures without knowing their details. However, software and hardware implementations of the TM model have proven to be limited when adopted in isolation. Hybrid transactional systems (HyTM) are the proposed solution to these problems, allowing applications to benefit from multicore machines. The flexibility of conventional hybrid systems, even though allowing simultaneous execution of hardware and software transactions, decrease the performance of both hardware and software and increase the complexity of the software component. In this direction, this work presents the first eficient implementation (PhTM*) of phase-based transactional system, a viable alternative to conventional HyTMs. PhTM* removes the aditional instrumentation of hardware transactions, necessary in other HyTMs, and can use any STM library to execute software transactions. The proposal is the first to use hardware transactional support, available in a real (not emulated) processor, to run hardware transactions. The results show that PhTM* is capable of always choosing the best suited mode for all STAMP applications. In fact, PhTM* showed the best overall performance and was about 12% better then HyTM-NOrec, a de facto baseline in HyTM evaluation. (AU) | |
| FAPESP's process: | 14/00534-8 - Using hardware transactional support to accelerate software transactional memory systems |
| Grantee: | João Paulo Labegalini de Carvalho |
| Support Opportunities: | Scholarships in Brazil - Master |