Enabling the multi-threaded simulation for models written in SystemC

Author(s)

Rodrigo Richard Cantos Faveri

• Document type: Master's Dissertation
• Press: Campinas, SP.
• Institution: Universidade Estadual de Campinas (UNICAMP). Instituto de Computação
• Defense date: 2010-10-25

Examining board members

Sandro Rigo; Roberto Andre Hexsel; Paulo Cesar Centoducatte

• Advisor: Sandro Rigo; Rodolfo Jardim de Azevedo

Abstract

SystemC is a modeling language for development of hardware systems, such SoCs (Systems-on-Chip) architectural models, and integrated with the methodology and library TLM (Transaction Level Modeling), it offers the required simulation platform infrastructure capable to simulate software and hardware in a fast way at different abstration levels. However, its single thread simulation kernel prevents it from utilizing the potential computing power of multi-core machines to speed up the simulation. With the complexity and the functionality of new circuits and applications size increasing and the time-to-market becoming shorter, the simulation speed-up is essential. In the present work, we introduce a new SystemC version, able to perform in multi-core machines and, consequently, with performance gains of 2.Ox to 22.029x to the original version on machines with 4 and 12 cores simulating platforms with 4 to 64 threads. Furthermore, changes were made on the TLM interfaces for parallel process can synchronize independently of SystemC events, and because the changes in the SystemC simulation kernel, Archc also had to be adapted for execute in a parallel simulation environment (AU)

• FAPESP's process: 08/07810-0 - Enabiling multi-threaded simulation of SystemC models
• Grantee: Rodrigo Richard Cantos Faveri
• Support Opportunities: Scholarships in Brazil - Master