Daniel Borges de Lazari

Summary Over 17 years of experience developing ASICs, FPGAs, and Hardware Systems. Engaged in several System-on-a-Chip (SoC) design phases such as System Architecture, RTL coding, Performance/Power Analysis, IP Integration, Synthesis, Module and Top-Level Functional Verification, Static Timing Analysis, chip layout, Gate-level simulation, FPGA prototyping and SW interface. Worldwide industry knowledge in areas of ASIC/FPGA design and flow, EDA tools, Digital Video, CPU/PC architectures, Imaging sensors, Mobile Computing, Low Power designs, Space devices, Networking (wired, wireless, and optical), and Industrial Automation. Specialties Team Lead on ASIC/FPGA designs. VHDL, ModelSim, STA, PrimeTime, Cadence Encounter, Verilog, Synopsys, Intel XScale, C, ARM, and AMBA. (Source: Lattes Curriculum)