| Full text | |
| Author(s): |
Morales, Catalina Munoz
;
Murari, Rafael
;
de Carvalho, Joao P. L.
;
Honorio, Bruno Chinelato
;
Baldassin, Alexandro
;
Araujo, Guido
;
Sousa, L
;
Roma, N
;
Tomas, P
Total Authors: 9
|
| Document type: | Journal article |
| Source: | EURO-PAR 2021: PARALLEL PROCESSING; v. 12820, p. 14-pg., 2021-01-01. |
| Abstract | |
Due to their fine-grained operations and low conflict rates, graph processing algorithms expose a large amount of parallelism that has been extensively exploited by various parallelization frameworks. Transactional Memory (TM) is a programming model that uses an optimistic concurrency control mechanism to improve the performance of irregular applications, making it a perfect candidate to extract parallelism from graph-based programs. Although fast Hardware TM (HTM) instructions are now available in the ISA extensions of some major processor architectures (e.g., Intel and ARM), balancing the usage of Software TM (STM) and HTM to compensate for capacity and conflict aborts is still a challenging task. This paper presents a Phased TM implementation for graph applications, called Graph-Oriented Transactional Memory (GoTM). It uses a three-state (HTM, STM, GLOCK) concurrency control automaton that leverages both HTM and STM implementations to speed-up graph applications. Experimental results using seven well-known graph programs and real-life workloads show that GoTM can outperform other Phased TM systems and lock-based concurrency mechanisms such as the one present in Galois, a state-of-the-art framework for graph computations. (AU) | |
| FAPESP's process: | 17/15236-0 - An Architecture for FPGA Acceleration of Stochastic Programming Algorithms |
| Grantee: | Catalina Munoz Morales |
| Support Opportunities: | Scholarships in Brazil - Doctorate |