Advanced search
Start date
Betweenand


A Terabit Hybrid FPGA-ASIC Platform for Switch Virtualization

Full text
Author(s):
Saquetti, Mateus ; Brum, Raphael M. ; Zatt, Bruno ; Pagliarini, Samuel ; Cordeiro, Weverton ; Azambuja, Jose R. ; IEEE Comp Soc
Total Authors: 7
Document type: Journal article
Source: 2021 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2021); v. N/A, p. 6-pg., 2021-01-01.
Abstract

The roll-out of technologies like 5G and the need for multi-terabit bandwidth in backbone networks requires networking companies to make significant investments to keep up with growing service demands. For lower capital expenditure and faster time-to-market, companies can resort to anything-as-a-service providers to lease virtual resources. Nevertheless, existing virtualization technologies are still lagging behind next-generation networks' requirements. This paper breaks the terabit barrier by introducing a hybrid FPGA-ASIC architecture to virtualize programmable forwarding planes. In contrast to existing solutions, our architecture involves an ASIC that multiplexes network flows between programmable virtual switches running in an FPGA capable of full and partial reconfiguration, enabling virtual switch hot-swapping. Our evaluation shows the feasibility of a switch virtualization architecture capable of achieving a combined throughput of 3.2 Tbps by having up to 26 virtual switch instances in parallel with low resource occupation overhead. (AU)

FAPESP's process: 20/05183-0 - SkyNet: towards smart data planes
Grantee:Luciano Paschoal Gaspary
Support Opportunities: Research Projects - Thematic Grants