ProfCounter: Line-Level Cycle Counter for Xilinx OpenCL High-Level Synthesis

Author(s)

Perina, Andre Bannwart ; Becker, Juergen ; Bonato, Vanderlei ; IEEE

• Document type: Journal article
• Source: 2019 26TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS); v. N/A, p. 4-pg., 2019-01-01.

Abstract

Wide adoption of Field-Programmable Gate Arrays for compute-intensive problems has always been barred by the complex development flow, requiring hardware expert staff and extensive exploration effort. With the recent developments in High-Level Synthesis, it is possible to use high-level languages (e.g. C, C++, OpenCL) to produce hardware projects with reasonable results. However, several software development assist tools are still absent or provided with limited functionalities. In this paper ProfCounter is presented, consisting of a module capable of providing fine-grain profiling by measuring the latency of inner segments of OpenCL kernels. Thus, developers are able to perform analyses of specific parts of the code which can assist on code optimisations, by considering complex interactions between the kernel and other modules (e.g. DDR memory, cache) where cycle-accurate simulators are not able to properly model. Results show that ProfCounter is able to measure the cycle count of OpenCL kernels segments in the Xilinx environment and its overhead does not scale according to hardware complexity nor with the amount of measurements. (AU)

• FAPESP's process: 18/22289-6 - High-level mapping framework for heterogeneous architectures with FPGAs and GPUs
• Grantee: Andre Bannwart Perina
• Support Opportunities: Scholarships abroad - Research Internship - Doctorate (Direct)
• FAPESP's process: 16/18937-7 - Energy-aware design space exploration framework for heterogeneous architectures with FPGAs and GPUs
• Grantee: Andre Bannwart Perina
• Support Opportunities: Scholarships in Brazil - Doctorate (Direct)