| Full text | |
| Author(s): |
Menotti, Ricardo
;
Cardoso, Joao M. P.
;
Fernandes, Marcio M.
;
Marques, Eduardo
;
IEEE
Total Authors: 5
|
| Document type: | Journal article |
| Source: | IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE 2010); v. N/A, p. 6-pg., 2010-01-01. |
| Abstract | |
This paper presents the use of LALP to implement typical industrial application kernels, ADPCM Encoder and Decoder, in FPGAs. LALP is a domain specific language and its compilation framework aims to the direct mapping of algorithms originally described in a high-level language onto FPGAs. In particular, LALP focuses on loop pipelining, a key technique for the design of hardware accelerators. While the language syntax resembles C, it contains certain constructs that allow programmer interventions to enforce or relax data dependences as needed, and so optimize the performance of the generated hardware. We present experimental results showing significant performance gains using this approach, while still keeping the language syntax and semantics close to popular high level software languages, a desirable feature when considering time to market constraints. We believe the performance gains observed for the ADPCM implementation can be extended to other industrial applications relying on algorithms spending most of their execution time on loop structures, such signal and image processing. (AU) | |
| FAPESP's process: | 08/57870-9 - Critical Embedded Systems Institute |
| Grantee: | Jose Carlos Maldonado |
| Support Opportunities: | Research Projects - Thematic Grants |