| Full text | |
| Author(s): |
Guedes, Marcelo
;
Auler, Rafael
;
Duenha, Liana
;
Bonin, Edson
;
Azevedo, Rodolfo
Total Authors: 5
|
| Document type: | Journal article |
| Source: | JOURNAL OF SYSTEMS ARCHITECTURE; v. 59, n. 8, p. 12-pg., 2013-09-01. |
| Abstract | |
The design complexity of integrated circuits requires techniques that automate and ease common tasks, allowing developers to keep up with the rapid growth and demand of the industry. This paper presents acSynth, an integrated framework for development and synthesis based on ArchC ADL descriptions and introduces a new power characterization method at the architectural level. The acSynth is composed of a characterization tool used to extract the energy consumption behavior of processors and also of a simulation method that, after characterization, is able to estimate software energy consumption at high speeds. Our experimental results show the power figures obtained by the characterization flow of Plasma and Leon3 processors, a MIPS-I and SPARCv8 HDL descriptions, respectively, using two different synthesis tools: Xilinx Xpower and Altera PowerPlay. The acSynth simulator used these power figures to allow power analysis at more than 35 million instructions per second in a simulation with small accuracy diversion and without loss of generality. The system executes large tests in minutes, which would otherwise take years in standard HDL methodologies. (C) 2013 Elsevier B.V. All rights reserved. (AU) | |
| FAPESP's process: | 10/02230-5 - ADL based automatic generation of compiler backends |
| Grantee: | Rafael Auler |
| Support Opportunities: | Scholarships in Brazil - Master |
| FAPESP's process: | 11/09630-1 - Efficient emulation techniques for the Open-ISA instruction set architecture |
| Grantee: | Rafael Auler |
| Support Opportunities: | Scholarships in Brazil - Doctorate |
| FAPESP's process: | 11/00901-2 - Algorithms and hardware support for efficient virtual machines |
| Grantee: | Edson Borin |
| Support Opportunities: | Regular Research Grants |