Analysis of Single-Event Upsets in a Microsemi ProAsic3E FPGA

Author(s):Show less -

Villa, Paulo R. C. ; Goerl, Roger C. ; Vargas, Fabian ; Poehls, Leticia B. ; Medina, Nilberto H. ; Added, Nemitala ; de Aguiar, Vitor A. P. ; Macchione, Eduardo L. A. ; Aguirre, Fernando ; da Silveira, Marcilei A. G. ; Bezerra, Eduardo A. ; IEEE

• Document type: Journal article
• Source: 2017 18TH IEEE LATIN AMERICAN TEST SYMPOSIUM (LATS 2017); v. N/A, p. 4-pg., 2017-01-01.

Abstract

The desirable use of Field-Programmable Gate Arrays (FPGAs) in aerospace & defense field has become a general consensus among IC and embedded system designers. Radiation-hardened (rad-hard) electronics used in this domain is regulated under severe and complex political and commercial treaties. In order to refrain from these undesired political and commercial barriers COTS FPGAs (despite the fact of their low reliability) have been considered as a promising alternative to replace radhard ICs. Moreover, SRAM-based FPGAs are pretermitted with respect to flash or anti-fuse devices. In this scenario, this paper analyses, by means of heavy-ion accelerator experiments, the Single-Event Upset (SEU) tolerance of the Microsemi ProAsic3E A3PE1500 COTS FPGA. This component is under pre-qualification process for use in some satellites of the Brazilian Space Program. Preliminary results are herein briefly presented and discussed. These experimental results allow us to consider this component as a strong candidate to replace rad-hard FPGAs, if its use is combined with strict system-level fault-tolerant strategies for error detection and correction . (AU)

• FAPESP's process: 12/03383-5 - Development of methodology for radiation tests on electronic components
• Grantee: Nilberto Heder Medina
• Support Opportunities: Regular Research Grants