Analysis of Low-Dropout Voltage Regulator designed with Gate-All-Around nanosheet transistors

Author(s)

de Barros Souto, Rayana Carvalho ; Martino, Joao Antonio ; Agopian, Paula Ghedini Der

• Document type: Journal article
• Source: 2023 37TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES, SBMICRO; v. N/A, p. 4-pg., 2023-01-01.

Abstract

In this work the Low Dropout Voltage Regulator (LDO) was designed with gate-all-around nanosheet transistors (GAA-NSH). The simulation model was developed using Verilog-A code and the Look Up Table (LUT) was based on experimental data. The gm/ID of 10.5 V-1 was used for the differential pair in the LDO circuit, resulting in a dropout voltage of 340 mV through the power output transistor. The LDO designed with NSH transistors demonstrated promising results, such as an open-loop gain of 57 dB, a gain-bandwidth product of 52 MHz, and a power rejection rate of approximately -70 dB. (AU)

• FAPESP's process: 20/04867-2 - High energy physics and instrumentation with the LHC-CERN
• Grantee: Marcelo Gameiro Munhoz
• Support Opportunities: Special Projects