Operation of Stacked Nanowire and Nanosheet MOS Transistors in Cryogenic Temperatures

• Grant number: 23/08530-0
• Support Opportunities: Scholarships in Brazil - Master
• Effective date (Start): November 01, 2023
• Effective date (End): March 31, 2025
• Field of knowledge: Engineering - Electrical Engineering - Electrical Materials
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Giovanni Almeida Matos
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil

Abstract

Quantum computing emerged as a way to increase the processing power of machines, solving problems in a much shorter time interval than would be required by conventional computers. However, the fundamental cell of quantum computers, the Qbits, are only operational at extremely cryogenic temperatures, in the range of thousandths of Kelvin. Furthermore, Qbits require integration with control and error correction systems implemented in CMOS technology. For this integration to occur, several works have demonstrated that using circuits built in CMOS technology operating at temperatures between 77 K and 4 K instead of at room temperature offers less noise and, consequently, less need for noise correction error.The semiconductor industry owes much of its success to the ability to continually downsize the devices (basically transistors) that make up integrated circuits (chips). This decrease allows an increase in the number of transistors integrated into a single chip. It also enables reduced consumed power, the manufacture of memories with greater storage capacity, and the integration of new functionalities to the chip. The constant miniaturization of MOS transistors, reaching tens of nanometers in channel length, has hindered the use of traditional MOS technologies manufactured on monocrystalline Si substrates due to the presence of short channel effects. Undesirably, such effects move the MOS transistor away from its ideal electrical characteristics, promoting an increase in the shutdown current and a reduction in the threshold voltage and subthreshold slope, among other problems. To minimize short-channel effects resulting from miniaturization, multi-gate MOS transistors, such as FinFETs, began to be used since they significantly improve the electrostatic control of charges in the channel region. Recently developed Si nanowire and nanosheet MOS transistors have shown promising results for the evolution of FinFETs. These structures have a cross-section of a few nanometers (generally 10 to 20 nanometers), allowing excellent electrostatic control in MOS transistors with channel lengths smaller than 14 nanometers. Also recently proposed are MOS transistors of nanowires and nanosheets stacked transistors, which consist of two or more superimposed semiconductor levels and share the same gate electrode, functioning as a single transistor, increasing the current per unit area consumed in the blade.In this context, this research project aims to expose the structures of nanowire and nanosheet MOS transistors to the appropriate temperature range for interface circuits with Qbits, evaluating their performance. This exhibition will allow obtaining relevant data for I) the evolution of these transistors for operation at cryogenic temperatures; II) the adaptation of the numerical simulation models to support the performance of simulations at cryogenic temperatures, allowing the observation of internal variables relevant to the transistors. The project will use stacked Si nanowires or nanosheet MOS transistors manufactured at CEA-Leti, France.