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Atomistic simulation of nanowire MOSFETs electrical properties

Grant number: 19/15500-5
Support Opportunities:Regular Research Grants
Duration: January 01, 2020 - March 31, 2023
Field of knowledge:Engineering - Electrical Engineering - Electrical Materials
Convênio/Acordo: CONFAP - National Council of State Research Support Foundations
Principal Investigator:Marcelo Antonio Pavanello
Grantee:Marcelo Antonio Pavanello
Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil
Associated researchers: Alan Carlos Junior Rossetto ; Fábio Fedrizzi Vidor ; Michelly de Souza ; Renan Trevisoli Doria ; Rodrigo Trevisoli Doria ; Thiago Hanna Both ; Vinícius Valduga de Almeida Camargo
Associated grant(s):23/03006-1 - EUROSOI-ULIS 2023 - Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, AR.EXT

Abstract

The semiconductor industry owes much of its success to the ability of continually downscale the devices (basically transistors) that make the integrated circuits (chips). This decrease in the size of the devices allows an increase in the number of transistors integrated in a single chip. It also allows the reduction of the dissipated power, larger memories and integration of new functionalities to the chip. As a way to minimize the degradation of the electrical properties of the MOS transistors due to miniaturization, MOS structures with multiple gates are now used, since they significantly improve the electrostatic control of the charges in the channel region. Multiple-gate transistors have gained a lot of attention from the scientific community. Another multiple-gate structure, recently developed and that has presented promising results, is the nanowire MOS transistor. These structures have a cross section of few nanometers, allowing excellent electrostatic control and minimizing undesirable effects in MOS transistors with channel lengths of the order of 10 nanometers. In transistors with nanometer dimensions, a single atom or electron can influence the electrical behavior of the transistor. Technologically, it is impractical or extremely difficult to control the manufacturing process of semiconductors on an atomic scale. Thus, it is more appropriate to realize the design of integrated circuits in order to tolerate variations in the electrical behavior of the transistors that compose it. For that, models and simulators are needed that can predict the electric behavior and the associated variations. Therefore, simulation models and techniques should consider this new stochastic nature of transistor behavior. The materials used have imperfections, defects or traps that can capture electrons that should contribute to the conduction of electric current. This leads to reliability problems, since the behavior of these traps can lead to a change in the performance and response of the electric circuit over time. A problem for the simulation of nanometer size MOS structures is the need to include quantum effects, which modify the centroid of electrons to the depth of the semiconductor, a few nanometers below the interface between the silicon and the door insulation. In these cases, commercial numerical simulation tools, which are based on the semi-classical approach of electric current conduction by the diffusion and drift mechanisms, do not allow the inclusion of these effects with precision. One way to perform simulations that are more realistic is the adoption of atomistic (or particle) simulation tools. In these tools, the electric current scattering events are determined probabilistically, without the initial assumption of conduction by the diffusion and drift mechanisms. In this context, a three-dimensional simulator of Monte Carlo devices, based on non-isothermal particles, was developed in a collaboration between the groups participating in this proposal, which is fully functional for planar structures. This collaborative research project aims to enhance the atomistic simulation tool, enabling it to simulate nanowire MOS transistors. The results of the atomistic simulations will be compared with experimental results, deepening the knowledge about the electrical properties of nanowires MOS transistors, when submitted to conditions of variable temperature. For validation of the atomistic simulator, electrical measurements will be used nanowires MOS transistors. Three-dimensional numerical simulations using semi-classical techniques will also be used for comparison with atomistic simulations. (AU)

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Scientific publications (35)
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
SILVA, EVERTON M.; TREVISOLI, RENAN; DORIA, RODRIGO T.. Junctionless nanowire transistors effective channel length extraction through capacitance characteristics. Solid-State Electronics, v. 208, p. 5-pg., . (19/15500-5)
SILVA, LUCAS MOTA BARBOSA DA; PAVANELLO, MARCELO ANTONIO; CASSE, MIKAEL; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; DE SOUZA, MICHELLY. Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors. Solid-State Electronics, v. 208, p. 4-pg., . (23/03006-1, 19/15500-5)
BARBOSA DA SILVA, LUCAS MOTA; PAVANELLO, MARCELO ANTONIO; CASSE, MIKAEL; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; DE SOUZA, MICHELLY; IEEE. Analysis of Variability in Transconductance and Mobility of Nanowire Transistors. 2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022), v. N/A, p. 4-pg., . (19/15500-5)
COSTA, FERNANDO J.; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Ultra-Low-Power Diodes Composed by SOI UTBB Transistors. 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., . (19/15500-5)
TREVISOLI, RENAN; PAVANELLO, MARCELO A.; DORIA, RODRIGO T.; CAPOVILLA, CARLOS E.; BARRAUD, SYLVAIN; DE SOUZA, MICHELLY. Variability Modeling in Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 69, n. 8, p. 7-pg., . (19/15500-5)
RODRIGUES, JAIME C.; MARINIELLO, GENARO; CASSE, MIKAEL; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A.; IEEE. Temperature Influence on the Electrical Properties of Vertically Stacked Nanowire MOSFETs. 35TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO2021), v. N/A, p. 4-pg., . (19/15500-5)
GRAZIANO JUNIOR, NILTON; COSTA, FERNANDO J.; TREVISOLI, RENAN; BARRAUD, SYLVAIN; DORIA, RODRIGO T.. Influence of interface traps density and temperature variation on the NBTI effect in p-Type junctionless nanowire transistors. Solid-State Electronics, v. 186, . (19/15500-5)
FONTE, E. T.; TREVISOLI, R.; DORIA, R. T.; IEEE. Charge Pumping-Based Method for Traps Density Extraction in Junctionless Transistors. 2021 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., . (19/15500-5)
DE SOUZA, MICHELLY; CERDEIRA, ANTONIO; ESTRADA, MAGALI; BARRAUD, SYLVAIN; CASSE, MIKAEL; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A.; IEEE. Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures. 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., . (19/15500-5)
DA FONTE, EWERTON TEIXEIRA; TREVISOLI, RENAN; BARRAUD, SYLVAIN; DORIA, RODRIGO T.. Interface traps density extraction through transient measurements in junctionless transistors. Solid-State Electronics, v. 194, p. 6-pg., . (19/15500-5)
AUGUSTO RIBEIRO, THALES; CERDEIRA, ANTONIO; ESTRADA, MAGALI; BARRAUD, SYLVAIN; ANTONIO PAVANELLO, MARCELO. Pragmatic evaluation of fin height and fin width combined variation impact on the performance of junctionless transistors. JOURNAL OF COMPUTATIONAL ELECTRONICS, v. 21, n. 3, p. 12-pg., . (16/10832-1, 19/15500-5)
DE SOUZA, MICHELLY; DORIA, RODRIGO T.; TREVISOLI, RENAN; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks. IEEE TRANSACTIONS ON NANOTECHNOLOGY, v. 20, p. 234-242, . (19/15500-5, 14/18041-8)
RIBEIRO, THALES AUGUSTO; BERGAMASCHI, FLAVIO ENRICO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Influence of fin width variation on the electrical characteristics of n-type junctionless nanowire transistors at high temperatures. Solid-State Electronics, v. 185, . (16/10832-1, 19/15500-5)
SHIBUTANI, ANDRE B.; DE SOUZA, MICHELLY; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Junctionless Nanowire Transistors Based Wilson Current Mirror Configuration. 2021 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., . (19/15500-5)
MARINIELLO, GENARO; BARRAUD, SYLVAIN; VINET, MAUD; CASSE, MIKAEL; FAYNOT, OLIVIER; CALCADE, JAIME; PAVANELLO, MARCELO ANTONIO. Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K. Solid-State Electronics, v. 194, p. 7-pg., . (19/15500-5)
CERDEIRA, ANTONIO; ESTRADA, MAGALI; MARINIELLO DA SILVA, GENARO; CALCADE RODRIGUES, JAIME; PAVANELLO, MARCELO A.; IEEE. Modeling of silicon stacked nanowire and nanosheet transistors at high temperatures. 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., . (19/15500-5)
GRAZIANO JUNIOR, N.; TREVISOLI, R.; DORIA, R. T.; IEEE. NBTI Dependence on Temperature in Junctionless Nanowire Transistors. 35TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO2021), v. N/A, p. 4-pg., . (19/15500-5)
RIBEIRO, THALES AUGUSTO; BARRAUD, SYLVAIN; BERGAMASCHI, FLAVIO ENRICO; PAVANELLO, MARCELO ANTONIO; IEEE. Influence of Fin Width Variation on the Electrical Characteristics of n-Type Junctionless Nanowire Transistors at High Temperatures. 2020 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., . (16/10832-1, 19/15500-5)
RIBEIRO, THALES AUGUSTO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Analysis of the Electrical Parameters of SOI Junctionless Nanowire Transistors at High Temperatures. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v. 9, p. 492-499, . (16/10832-1, 19/15500-5)
RODRIGUES, JAIME C. C.; MARINIELLO, GENARO; CASSE, MIKAEL; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A. A.. Electrical characterization of stacked SOI nanowires at low temperatures. Solid-State Electronics, v. 191, p. 7-pg., . (19/15500-5)
DA COSTA, FERNANDO JOSE; TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI. Cross-coupling effects in common-source current mirrors composed by UTBB transistors. Solid-State Electronics, v. 194, p. 5-pg., . (19/15500-5)
COSTA, FERNANDO J.; TREVISOLI, RENAN; DORIA, RODRIGO T.. Thermal cross-coupling effects in side-by-side UTBB-FDSOI transistors. Solid-State Electronics, v. 185, . (19/15500-5)
PRATES, RHAYCEN R.; BARRAUD, SYLVAIN; CASSE, MIKAEL; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A.; IEEE. Experimental Comparison of Junctionless and Inversion-Mode Nanowire MOSFETs Electrical Properties at High Temperatures. 2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022), v. N/A, p. 4-pg., . (19/15500-5)
BERGAMASCHI, F. E.; PAVANELLO, M. A.. TCAD Evaluation of the Active Substrate Bias Effect on the Charge Transport of Omega-Gate Nanowire MOS Transistors With Ultra-Thin BOX. IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, v. 10, p. 7-pg., . (19/15500-5)
SHIBUTANI, ANDRE B.; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Junctionless Nanowire Transistor for Analog Applications: Cascode Current Mirror Configuration. 2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022), v. N/A, p. 4-pg., . (19/15500-5)
COSTA, FERNANDO J.; TREVISOLI, RENAN; CAPOVILLA, CARLOS EDUARDO; DORIA, RODRIGO T.; IEEE. Standard MOS Diodes Composed by SOI UTBB Transistors. 2022 36TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY (SBMICRO 2022), v. N/A, p. 4-pg., . (19/15500-5)
DE SOUZA, MICHELLY; RODRIGUES, JAIME CALCADE; MARINIELLO, GENARO; CASSE, MIKAEL; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A.; IEEE. An Experimental Evaluation of Fin Width and Low-Temperature Influence on GIDL in Stacked SOI Nanowires. 2022 IEEE 15TH WORKSHOP ON LOW TEMPERATURE ELECTRONICS (WOLTE 2022), v. N/A, p. 4-pg., . (19/15500-5)
BERGAMASCHI, F. E.; RIBEIRO, T. A.; PAZ, B. C.; DE SOUZA, M.; BARRAUD, S.; CASSE, M.; VINET, M.; FAYNOT, O.; PAVANELLO, M. A.. Experimental Demonstration of Omega-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 69, n. 7, p. 7-pg., . (19/15500-5)
BERGAMASCHI, FLAVIO E.; WIRTH, GILSON, I; BARRAUD, SYLVAIN; CASSE, MIKAEL; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A.; IEEE. Extraction of the Back Channel Mobility in SOI Nanowire MOS Transistors under Substrate Biasing. 2022 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., . (19/15500-5)
MARINIELLO, GENARO; DE CARVALHO, CESAR AUGUSTO BELCHIOR; PAZ, BRUNA CARDOSO; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analog characteristics of n-type vertically stacked nanowires. Solid-State Electronics, v. 185, . (19/15500-5)
ROSSETTO, ALAN; SOARES, CAROLINE; WIRTH, GILSON; PAVANELLO, MARCELO; WANG, ZIYI; VASILESKA, DRAGICA; IEEE. Thermal Evaluation of 28-nm p-type FD-SOI MOSFETs. 2023 IEEE LATIN AMERICAN ELECTRON DEVICES CONFERENCE, LAEDC, v. N/A, p. 4-pg., . (19/15500-5)
DE SOUZA, MICHELLY; CERDEIRA, ANTONIO; ESTRADA, MAGALI; CASSE, MIKAEL; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO A.. Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures. Solid-State Electronics, v. 208, p. 4-pg., . (19/15500-5, 23/03006-1)
BERGAMASCHI, F. E.; PAVANELLO, M. A.; IEEE. TCAD Evaluation of the Substrate Bias Influence on the Carrier Transport of O-Gate Nanowire MOS Transistors with Ultra-Thin BOX. 2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., . (19/15500-5)
PAVANELLO, MARCELO A.; RIBEIRO, THALES A.; CERDEIRA, ANTONIO; AVILA-HERRERA, FERNANDO; IEEE. Analytical Compact Model for Transcapacitances of Junctionless Nanowire Transistors. 2021 IEEE LATIN AMERICA ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., . (19/15500-5, 16/10832-1)
MARINIELLO, GENARO; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAZ, BRUNA CARDOSO; PAVANELLO, MARCELO ANTONIO; IEEE. Evaluation of Analog Characteristics of n-Type Vertically Stacked Nanowires. 2020 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., . (19/15500-5)

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