Electrical characterization and modeling of advanced electronic devices

• Grant number: 14/18041-8
• Support type: Scholarships in Brazil - Post-Doctorate
• Effective date (Start): November 01, 2014
• Effective date (End): October 31, 2017
• Field of knowledge: Engineering - Electrical Engineering
• Cooperation agreement: Coordination of Improvement of Higher Education Personnel (CAPES)
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Renan Trevisoli Doria
• Home Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil

Abstract

Advanced electronic devices such as Junctionless Nanowire Transistors (JNTs) have been developed aiming at a larger scaling of the devices in comparison with conventional MOSFETs, due to the better electrostatic control of the channel charges, minimizing the short-channel effects occurrence. Therefore, JNTs provide a better miniaturization of electronic devices.Aiming at the analysis of the device operation in electric circuits, analytical models are necessary. These models must be functional for transistors of different characteristics such as doping concentration and dimensions, operating at different biases and temperatures. The models should also comprise both static and dynamic behaviors. The later is related with the device intrinsic capacitances. However, the dynamic behavior of junctionless devices has barely been explored in the literature, specially the modeling of triple gate JNTs, which are the most important in terms of applications.Therefore, the main objective of this project is to model the dynamic behavior of electronic devices, focusing on the junctionless triple gate transistors. To develop the project, both numerical simulations and electrical characterization are necessary. The static behavior should also be analyzed, since it interferes in the charges distribution and in the capacitances. Other devices such as FinFETs and undoped nanowires may also be analyzed for comparison purposes. (AU)

Scientific publications

(9)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A. Junctionless nanowire transistors parameters extraction based on drain current measurements. Solid-State Electronics, v. 158, p. 37-45, AUG 2019. Web of Science Citations: 0.

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. MICROELECTRONIC ENGINEERING, v. 215, JUL 15 2019. Web of Science Citations: 0.

PAVANELLO, MARCELO ANTONIO; TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY. Static and dynamic compact analytical model for junctionless nanowire transistors. JOURNAL OF PHYSICS-CONDENSED MATTER, v. 30, n. 33 AUG 22 2018. Web of Science Citations: 3.

DORIA, RODRIGO T.; FLANDRE, DENIS; TREVISOLI, RENAN; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A. Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures. Semiconductor Science and Technology, v. 32, n. 9 SEP 2017. Web of Science Citations: 1.

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; CASSE, MIKAEL; REIMBOLD, GILLES; FAYNOT, OLIVIER; GHIBAUDO, GERARD; PAVANELLO, MARCELO ANTONIO. A New Method for Series Resistance Extraction of Nanometer MOSFETs. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 64, n. 7, p. 2797-2803, JUL 2017. Web of Science Citations: 4.

DORIA, RODRIGO TREVISOLI; TREVISOLI, RENAN; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, n. SI, p. 17-20, JUN 25 2017. Web of Science Citations: 4.

TREVISOLI, RENAN; DE SOUZA, MICHELLY; DORIA, RODRIGO TREVISOLI; KILCHTYSKA, VALERIYA; FLANDRE, DENIS; PAVANELLO, MARCELO ANTONIO. Junctionless nanowire transistors operation at temperatures down to 4.2K. Semiconductor Science and Technology, v. 31, n. 11 NOV 2016. Web of Science Citations: 4.

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; PAVANELLO, MARCELO ANTONIO. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, n. 2, p. 856-863, FEB 2016. Web of Science Citations: 9.

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; PAVANELLO, MARCELO ANTONIO. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors. MICROELECTRONIC ENGINEERING, v. 147, p. 23-26, NOV 1 2015. Web of Science Citations: 3.