Electrical characterization and modeling of advanced electronic devices

• Grant number: 14/18041-8
• Support Opportunities: Scholarships in Brazil - Post-Doctoral
• Start date: November 01, 2014
• End date: October 31, 2017
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Measurements, Instrumentation
• Agreement: Coordination of Improvement of Higher Education Personnel (CAPES)
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Renan Trevisoli Doria
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil

Abstract

Advanced electronic devices such as Junctionless Nanowire Transistors (JNTs) have been developed aiming at a larger scaling of the devices in comparison with conventional MOSFETs, due to the better electrostatic control of the channel charges, minimizing the short-channel effects occurrence. Therefore, JNTs provide a better miniaturization of electronic devices.Aiming at the analysis of the device operation in electric circuits, analytical models are necessary. These models must be functional for transistors of different characteristics such as doping concentration and dimensions, operating at different biases and temperatures. The models should also comprise both static and dynamic behaviors. The later is related with the device intrinsic capacitances. However, the dynamic behavior of junctionless devices has barely been explored in the literature, specially the modeling of triple gate JNTs, which are the most important in terms of applications.Therefore, the main objective of this project is to model the dynamic behavior of electronic devices, focusing on the junctionless triple gate transistors. To develop the project, both numerical simulations and electrical characterization are necessary. The static behavior should also be analyzed, since it interferes in the charges distribution and in the capacitances. Other devices such as FinFETs and undoped nanowires may also be analyzed for comparison purposes. (AU)

Scientific publications

(28)

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; BARRAUD, SYLVAIN; PAVANELLO, MARCELO ANTONIO. Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors. MICROELECTRONIC ENGINEERING, v. 215, JUL 15 2019. (14/18041-8)

DORIA, RODRIGO T.; FLANDRE, DENIS; TREVISOLI, RENAN; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.. Effect of the back bias on the analog performance of standard FD and UTBB transistors-based self-cascode structures. Semiconductor Science and Technology, v. 32, n. 9, SEP 2017. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; PAVANELLO, MARCELO ANTONIO. Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors. MICROELECTRONIC ENGINEERING, v. 147, p. 23-26, NOV 1 2015. (14/18041-8)

PAVANELLO, MARCELO ANTONIO; TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY. Static and dynamic compact analytical model for junctionless nanowire transistors. JOURNAL OF PHYSICS-CONDENSED MATTER, v. 30, n. 33, AUG 22 2018. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; CASSE, MIKAEL; REIMBOLD, GILLES; FAYNOT, OLIVIER; GHIBAUDO, GERARD; PAVANELLO, MARCELO ANTONIO. A New Method for Series Resistance Extraction of Nanometer MOSFETs. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 64, n. 7, p. 2797-2803, JUL 2017. (14/18041-8)

DE SOUZA, MICHELLY; DORIA, RODRIGO T.; TREVISOLI, RENAN; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. On the Application of Junctionless Nanowire Transistors in Basic Analog Building Blocks. IEEE TRANSACTIONS ON NANOTECHNOLOGY, v. 20, p. 234-242, 2021. (19/15500-5, 14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; PAVANELLO, MARCELO A.; IEEE. A New Series Resistance Extraction Method for Junctionless Nanowire Transistors. 2016 31ST SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2016-01-01. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.; BARRAUD, SYLVAIN; VINET, MAUD; IEEE. Influence of the Crystal Orientation on the Operation of Junctionless Nanowire Transistors. 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2016-01-01. (14/18041-8)

DORIA, RODRIGO T.; TREVISOLI, RENAN; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.; IEEE. Physical Insights on the Dynamic Response of Junctionless Nanowire Transistors. 2016 31ST SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2016-01-01. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.; IEEE. Accounting for Series Resistance in the Compact Model of Triple-Gate Junctionless Nanowire Transistors. 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2018-01-01. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.; IEEE. Analysis of p-type Junctionless Nanowire Transistors with Different Crystallographic Orientations. 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS, v. N/A, p. 4-pg., 2017-01-01. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO; BARRAUD, SYLVAIN; PAVANELLO, MARCELO; IEEE. Compact Analytical Model for Trap-Related Low Frequency Noise in Junctionless Transistors. 49TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC 2019), v. N/A, p. 4-pg., 2019-01-01. (14/18041-8)

COSTA, FERNANDO J.; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Analysis of the substrate effect by the capacitive coupling in SOI UTBB Transistors. 2019 34TH SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO 2019), v. N/A, p. 4-pg., 2019-01-01. (14/18041-8)

DORIA, R. T.; TREVISOLI, R.; DE SOUZA, M.; PAVANELLO, M. A.; FLANDRE, D.; IEEE. Use of Back Gate Bias to Improve the Performance of n- and p-Type UTBB Transistors-Based Self-Cascode Structures Applied to Current Mirrors. 2016 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2016-01-01. (14/18041-8)

COSTA, FERNANDO J.; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Thermal Cross-Coupling Effects Analysis in UTBB Transistors. 2020 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS), v. N/A, p. 4-pg., 2020-01-01. (14/18041-8)

COSTA, FERNANDO J.; TREVISOLI, RENAN; DE SOUZA, MICHELLY; DORIA, RODRIGO T.; IEEE. Analysis of the Thermal Properties of Self-Cascode Structures Composed by UTBB Transistors. LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC 2020), v. N/A, p. 4-pg., 2020-01-01. (14/18041-8)

COSTA, FERNANDO J.; PAVANELLO, MARCELO A.; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Analysis of the Substrate Bias Effect on the Thermal Properties of SOI UTBB Transistors. 2017 32ND SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO): CHIP ON THE SANDS, v. N/A, p. 4-pg., 2017-01-01. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.; BARRAUD, SYLVAIN; IEEE. A New Method for Junctionless Transistors Parameters Extraction. 2017 47TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE (ESSDERC), v. N/A, p. 4-pg., 2017-01-01. (14/18041-8)

DORIA, RODRIGO TREVISOLI; TREVISOLI, RENAN; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, n. SI, p. 17-20, JUN 25 2017. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; PAVANELLO, MARCELO A.. Junctionless nanowire transistors parameters extraction based on drain current measurements. Solid-State Electronics, v. 158, p. 37-45, AUG 2019. (14/18041-8)

TREVISOLI, RENAN; DE SOUZA, MICHELLY; DORIA, RODRIGO TREVISOLI; KILCHTYSKA, VALERIYA; FLANDRE, DENIS; PAVANELLO, MARCELO ANTONIO. Junctionless nanowire transistors operation at temperatures down to 4.2K. Semiconductor Science and Technology, v. 31, n. 11, NOV 2016. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO TREVISOLI; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; PAVANELLO, MARCELO ANTONIO. Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 63, n. 2, p. 856-863, FEB 2016. (14/18041-8)

TREVISOLI, RENAN; PAVANELLO, MARCELO ANTONIO; CAPOVILLA, CARLOS EDUARDO; BARRAUD, SYLVAIN; DORIA, RODRIGO TREVISOLI. Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors. IEEE TRANSACTIONS ON ELECTRON DEVICES, v. 67, n. 6, p. 2536-2543, JUN 2020. (14/18041-8)

DORIA, RODRIGO TREVISOLI; TREVISOLI, RENAN; DE SOUZA, MICHELLY; BARRAUD, SYLVAIN; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization. MICROELECTRONIC ENGINEERING, v. 178, p. 4-pg., 2017-06-25. (14/18041-8)

MOREIRA, CLAUDIO V.; TREVISOLI, RENAN; PAVANELLO, MARCELO ANTONIO; IEEE. Verilog-A Implementation of Static and Dynamic Trigate Junctionless Nanowire Transistor Compact Model. 2019 LATIN AMERICAN ELECTRON DEVICES CONFERENCE (LAEDC), v. N/A, p. 4-pg., 2019-01-01. (14/18041-8)

COSTA, FERNANDO J.; TREVISOLI, RENAN; DORIA, RODRIGO T.; IEEE. Analysis of the Output Conductance Degradation With the Substrate Bias in SOI UTB and UTBB Transistors. 2018 33RD SYMPOSIUM ON MICROELECTRONICS TECHNOLOGY AND DEVICES (SBMICRO), v. N/A, p. 4-pg., 2018-01-01. (14/18041-8)

TREVISOLI, R.; DORIA, R. T.; DE SOUZA, M.; PAVANELLO, M. A.; IEEE. Modeling the Interface Trap Density Influence on Junctionless Nanowire Transistors Behavior. 2018 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2018-01-01. (14/18041-8)

TREVISOLI, RENAN; DORIA, RODRIGO T.; DE SOUZA, MICHELLY; PAVANELLO, MARCELO A.; IEEE. Lateral Spacers Influence on the Effective Channel Length of Junctionless Nanowire Transistors. 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2017-01-01. (14/18041-8)