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Development heterojunction bipolar transistors (HBT) and Vertical MOS Transistors with InGaP/GaAs.

Grant number: 13/13983-2
Support type:Scholarships in Brazil - Doctorate
Effective date (Start): October 01, 2013
Effective date (End): September 30, 2017
Field of knowledge:Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits
Principal Investigator:Jose Alexandre Diniz
Grantee:Cassio Roberto de Almeida
Home Institution: Centro de Componentes Semicondutores (CCS). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil

Abstract

Semiconductors compounds of type III-V, such as gallium arsenide (GaAs) and indium phosphide (InP) are potentially used in electronic and optoelectronic circuits of high speed, because these semiconductors have several advantages, as high electron mobility (greater than 5,400 cm2 / V · s), high saturation velocity and energy bands with direct transition when compared with the semiconductor silicon (Si). Furthermore, they make possible the manufacture of a variety of heteroestruturas such as InGaP / GaAs, which may result in monolithic integration of optical and electronic functions. In view of the wide applicability of heterojunction bipolar transistors (HBT) and recent, but promising investigations of vertical transistors, this work aims to obtain the characterization and development of manufacturing steps transistors HBTs type InGaP / GaAs self-aligned, which present the final characteristics of high frequency, as well to investigate the feasibility of design, fabrication and characterization of MOS transistors with vertical InGaP / GaAs. It also includes the study and development of the growth of epitaxial layers of the structure InGaP / GaAs, allowing the formation of interfaces with a minimum density of defects. The differential is the use of a particular mask set. In this new set of masks will be a greater variety of sizes emitter, besides having a reduced number of process steps. Following this line of reasoning, the increasing miniaturization of electronic devices has hindered the use of MOS transistors in planar technology with nanometer dimensions, due to the presence of short channel effects. Important advantages corroborate the use and improvement of the technology of vertical MOS transistor, among them the length of scale of the channel not to be limited by thethe minimum resolution lithographic, the increased power and the reduced size allows the use of side walls of 3D trench to form the channel of the transistor, which consequently favor a current drain and a much higher operating frequency compared to planar MOS transistor. Some manufacturing steps of the conventional process of manufacturing MOS transistors, for example the ion implantation, can not be used to control the threshold voltage of a MOS transistor vertical. A new method for diffusing impurities into a film deposited by CVD (Chemical Vapor Deposition) is designed to adjust the threshold voltage of the vertical MOS transistor, in order to make manufacturing of vertical MOS transistors viable in GaAs, since one of the main challenges today is to improve the performance of the architectures based on metal-oxide-semiconductor devices by implementing advanced structures and non-classical (based only on silicon). Additionally, the use of devices with more than one gate electrode has emerged as one promising alternative technology for maintaining a continuous reduction in the dimensions of the MOS transistors. Performing will be the study and development of models and schematics equivalent of transistor HBT InGaP / GaAs and vertical MOS transistors, and will be carried to characterize and to evaluation of the performance of these structures through measures DC and AC, RF measurements and curves of signal noise, besides the use of analytical models available in the literature to explain the observed effects and comparison of performance relative to other transistors InGaP / GaAs constructed using different masks.

Academic Publications
(References retrieved automatically from State of São Paulo Research Institutions)
ALMEIDA, Cassio Roberto de. Fabrication and characterization of HBT, vertical MOSFET, JNT and TFET transistors based on III-V substrates with silicon nitride passivation. 2019. Doctoral Thesis - Universidade Estadual de Campinas, Faculdade de Engenharia Elétrica e de Computação.

Please report errors in scientific publications list by writing to: cdi@fapesp.br.