Electrical characterization and tridimensional simulation of nanowires MOS transistors

• Grant number: 16/06301-0
• Support Opportunities: Scholarships abroad - Research Internship - Doctorate
• Start date: September 05, 2016
• End date: September 04, 2017
• Field of knowledge: Engineering - Electrical Engineering - Electrical Materials
• Principal Investigator: Marcelo Antonio Pavanello
• Grantee: Bruna Cardoso Paz
• Supervisor: Casse Mikael
• Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil
• Institution abroad: Commissariat à l'énergie atomique et aux énergies alternatives (CEA), France
• Associated to the scholarship: 15/10491-7 - Electrical characterization and tridimensional simulation of nanowires MOS transistors, BP.DR

Abstract

This project aims to sustain an international cooperation between the research group coordinated by Prof. Dr. Marcelo Antonio Pavanello, from Department of Electrical Engineering of Centro Universitário da FEI, situated in São Bernardo do Campo, Brazil, and the research group coordinated by Dr. Gilles Reimbold and Dr. Mikaël Cassé, from the Laboratoire d'électronique et de technologie de l'information (Leti), situated in Grenoble, France. While Leti is one of the few research centers in the world capable of fabricating aggressively scaled devices, such as nanowires MOSFETs, the research group of Prof. Dr. Pavanello is the first and the only one in Brazil studying ultra-scaled nanowires, through Ms. Paz work.The main focus of the project will be the electrical characterization and tridimensional advanced simulations of nanowires MOSFETs implemented in Silicon-On-Insulator technology. The project will be conducted by Mrs. Paz as a part of her Ph. D. thesis at FEI, in a stay of 12 months at Leti. During her stay Mrs. Paz will work with nanowires MOSFETs considering strained and unstrained transistors, different silicon and silicon-germanium bonds and wide ranges for channel length and channel width. Cryogenic operation at low temperature down to 4K will be also explored as one of the main subjects.The stay at Leti will be of main interest in her Ph. D. work as she will be able to experimentally study some of the main candidates for the next technological nodes, those cannot be found in other place but an advanced research center such as Leti. (AU)

Scientific publications

(The scientific publications listed on this page originate from the Web of Science or SciELO databases. Their authors have cited FAPESP grant or fellowship project numbers awarded to Principal Investigators or Fellowship Recipients, whether or not they are among the authors. This information is collected automatically and retrieved directly from those bibliometric databases.)

PAZ, BRUNA CARDOSO; PAVANELLO, MARCELO ANTONIO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; SARAFIS, P; NASSIOPOULOU, AG. Performance and Transport Analysis of Vertically Stacked p-FET SOI Nanowires. 2017 JOINT INTERNATIONAL EUROSOI WORKSHOP AND INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION ON SILICON (EUROSOI-ULIS 2017), v. N/A, p. 4-pg., 2017-01-01. (15/10491-7, 16/06301-0)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO. Electrical characterization of vertically stacked p-FET SOI nanowires. Solid-State Electronics, v. 141, p. 84-91, MAR 2018. (15/10491-7, 16/06301-0)

PAZ, BRUNA CARDOSO; CASSE, MIKAEL; BARRAUD, SYLVAIN; REIMBOLD, GILLES; VINET, MAUD; FAYNOT, OLIVIER; PAVANELLO, MARCELO ANTONIO; IEEE. New method for individual electrical characterization of stacked SOI nanowire MOSFETs. 2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S), v. N/A, p. 3-pg., 2017-01-01. (15/10491-7, 16/06301-0)