The constant miniaturization of MOS transistors has hindered the use of traditional technologies in Si substrates, due to the occurrence of short channel effects, which degrade the electrical characteristics of the transistors. The manufacturing technology of integrated circuits (ICs) in SOI wafers has been constituted as an important alternative to conventional CMOS technology, in the production of ICs, aiming at the continuous reduction of dimensions. SOI transistors are made in a thin layer of silicon, separated from the substrate by an insulating material, and present improvements such as reduction in junction capacitances and larger carrier mobility in the channel region, minimizing or delaying for more complex technological generations, the occurrence of undesirable parasitic effects, resulting from the reduction of the dimensions of MOSFETs. More recently, in order to minimize the effects of miniaturization, MOS transistors with multiple gates have been used. These devices have been considered quite promising, as they improve the electrostatic control of charges in the channel region, reducing the incidence of short channel effects. The reduction of silicon fin hight gave rise to nanowire transistors, which have a cross section of a few nanometers, allowing excellent electrostatic control and minimizing undesirable effects found in MOSFETs with channel lengths of the order of 10 nm. To increase the integration density, it is even possible to manufacture stacked nanowire transistors, increasing the current density per unit area.The analysis of the influence of temperature on the operation of electronic devices is of great importance because, when subjected to temperature variations, they present significant changes in their electrical behavior, which can impair or improve the functioning of ICs. The operation of MOS transistors at low temperatures offers improved performance compared to room temperature, and is of great importance in applications such as aerospace and quantum computing. On the other hand, despite the electrical performance degradation caused by operation at high temperatures, some applications such as automotive, expose transistors to high temperatures. In this way, the emergence of new applications and the need to develop robust technologies drives the study of electronic components and circuits at extreme operating temperatures.Threshold voltage is one of the basic electrical parameters of MOSFETs. There are several methods for extracting this parameter, based on both current and capacitance curves as a function of the device's gate voltage. However, it is known that these methods can result in different threshold voltage values for the same device, in addition to presenting differences in its dependence on temperature.In this project a study of the threshold voltage of nanowires SOI transistors of nanometric dimensions, as a function of temperature will be performed. The study will be carried out through electrical measurements and three-dimensional numerical simulations. Electrical measurements will allow obtaining the threshold voltage for several temperatures, using different extraction methods. The influence of nanowire width will be evaluated, in single-level and stacked transistors. Nanowire transistors manufactured at CEA-Leti/France will be used for electrical measurements. The three-dimensional numerical simulations will be calibrated with the experimental data and will allow the analysis of internal variables, such as electron potential and concentration, in order to determine the threshold voltage value through these physical variables. Thus, it is expected to determine which method available in the literature is more accurate to describe the physical behavior of the threshold voltage as a function of the nanowire width and temperature.
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