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Influence of Technological and Geometrical Parameters on the Performance of Graded-Channel SOI Transistors

Grant number: 12/24185-7
Support type:Scholarships in Brazil - Master
Effective date (Start): March 01, 2013
Effective date (End): February 28, 2015
Field of knowledge:Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Measurements, Instrumentation
Principal Investigator:Michelly de Souza
Grantee:Rafael Assalti
Home Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil


Silicon-On-Insulator technology constitutes an important alternative to sustain the continuous downscaling of standard CMOS technology. Nowadays, several studies can be found in the literature, regarding the operation of digital circuits with SOI transistors. However, few works report the potential of this technology for high performance analog circuits and devices. Despite of these advantages, SOI transistors present reduced drain breakdown voltage, due to floating body effect that activates the parasitic bipolar transistor inherent to the MOS transistor. Aiming at reducing the occurrence of parasitic bipolar effects and improving the analog performance of SOI transistor, increasing the breakdown voltage, a new structure, called Graded-Channel (GC) transistor, has been proposed. Several works report the advantages of this structure for analog applications, both at device and circuit level. The first GC SOI transistors reported in the literature were implemented in thin-film SOI technology, with fully depleted channel region. Although this technology presents several advantages, partially depleted (PD) technology presents high maturity level and has been already used to implement high performance commercial circuits. Recently, GC SOI transistors were successfully implemented in a PD SOI technology, also showing improved analog performance in comparison to uniformly doped counterpart. Recent results of GC SOI transistors have shown that, for a given technology, there exists a certain length for the lightly doped region which, independently of the total channel length, propitiates larger intrinsic voltage gain rise, in comparison to na uniformly doped transistor with similar total dimensions.In this work, a study of the influence of technological and geometrical parameters on the performance of GC SOI transistors will be performed. Special focus will be given to the analog characteristics of these devices. Electrical characterization of transistors implemented in two different SOI technologies will be performed. Besides, numerical process and device simulations will be carried out, varying silicon thickness and doping concentration level, as well as the channel length and length of the lightly doped regions, aiming at extend the analysis to more recent technologies.