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Nanowire transistors development in SOI substrates with nanometric thicknesses

Grant number: 12/13499-0
Support type:Scholarships in Brazil - Doctorate
Effective date (Start): September 01, 2012
Effective date (End): December 31, 2016
Field of knowledge:Engineering - Electrical Engineering
Principal Investigator:Marcelo Antonio Pavanello
Grantee:Juliana Pinheiro Nemer
Home Institution: Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil
Associated research grant:08/05792-4 - Design, fabrication and characterization of FinFET transistors, AP.TEM

Abstract

Currently, a series of studies reported in the literature indicate the technology Silicon-on-Insulator (Silicon-On-Insulator - SOI) as an important substitute for conventional MOS technology in the manufacture of transistors with reduced channel length. It is an important alternative to support the continuous size reduction faced by CMOS technology. The use of SOI technology provides improvements such as reduced junction capacitances and larger carrier mobility in the channel region, minimizing or slowing to more complex technological generations , the occurrence of undesirable parasitic effects that affect the performance of the MOS transistor.Although it has several advantages compared with conventional CMOS technology, and recently is already adopted by most semiconductor industries in the world for the implementation of integrated circuits for high density and complexity, such as microprocessors and memories it does not exist in our country universities or industries carrying out the fabrication of devices and circuits in CMOS SOI technology.This project aims to accomplish the design, fabrication and electrical characterization of thin-film SOI technology, with high-k dielectric and metal gate, for low power applications in Brazil. Initially, the design of this process will be done by two-dimensional numerical simulations, and a new set of photomasks will be developed. These two steps will be developed in the Centro Universitário da FEI. Then, the fabrication process designed will be implemented in facilities of Centro de Componentes Semicondutores from Unicamp and the resulting devices will be electrically characterized at Centro Universitário da FEI. The Centro Universitário da FEI and the Componentes Semicondutores da Unicamp act jointly in the project "PROJECT AND FABRICATION OF A THIN FILM SOI CMOS TECHNOLOGY FOR FOR LOW POWER APPLICATIONS "(CNPq project 552537/2011-0). Through this project was an agreement signed between the Componentes Semicondutores da UNICAMP, coordinated by Prof. Dr. José Alexandre Diniz, and Centro Universitário da FEI, allowing the fabrication of the devices proposed at CCS-Unicamp.Thus, as a main result of this project, the most important alternative technology for the fabrication of CMOS circuits will be made available to the national research community of microelectronics. To develop this project, work on developing the materials employed, the union of several fabrication processes for obtaining a CMOS technology, simulation and project of technology, among others, will be triggered, promoting cooperation and exchange faculty and students between the institutions involved.