Nanometric semiconductor devices projects

• Grant number: 16/24949-8
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: April 01, 2017
• End date: January 31, 2019
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits
• Principal Investigator: Maria Glória Caño de Andrade
• Grantee: Luis Felipe de Oliveira Bergamim
• Host Institution: Instituto de Ciência e Tecnologia. Universidade Estadual Paulista (UNESP). Campus de Sorocaba. Sorocaba , SP, Brazil

Abstract

The proposed project is a contribution for technological development of micro and nanoelectronics in Brazil, since it seeks to intend to research advanced semiconductor devices. These devices are promising structures with manometric dimensions and non-planar structures, such as Bulk, DTMOS and SOI transistors with multiple gate (also called FinFET or 3D transistor), and planar structures with extremely thin buried oxide called UTBOX (Ultra thin Buried Oxide) produced with new types of materials, innovative techniques of manufacturing, different sizes and configurations which will replace the currently used devices. The main goal of this work is the study of nanometric transistors with different channel engineering and gate dielectric. This study will be done through numerical simulations. The methodology for the development of this work consists of three main parts. Firstly, the structure will be constructed in a virtual environment to be possible to perform numerical simulations. In this project part, the simulations will have the goal of getting the trends of the main electrical characteristics of devices. In the second part, the simulations will be calibrated from the results of the measurements obtained in the in the Interuniversity Microelectronics Center (Imec/Belgium) of Catholic University Leuven. Finally, with the simulator calibrated, several simulations in order to understand/find the physical mechanisms involved in this type of devices. (AU)