|Support type:||Scholarships in Brazil - Master|
|Effective date (Start):||February 01, 2013|
|Effective date (End):||January 31, 2015|
|Field of knowledge:||Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits|
|Principal Investigator:||Salvador Pinillos Gimenez|
|Grantee:||Enrico Davini Neto|
|Home Institution:||Campus de São Bernardo do Campo. Centro Universitário da FEI (UNIFEI). Fundação Educacional Inaciana Padre Sabóia de Medeiros (FEI). São Bernardo do Campo , SP, Brazil|
Countless efforts and investments are being employed in order to reduce the dimensions of MOSFETs (Moore's Law) and furthermore to improve its current drain capability. A highly innovative approach to achieving that, yet not much explored by the scientific society, is by engineering strategies in the interface between the drain and channel regions, and between the channel and source regions of the MOSFETs, which could be simply translated into the study of innovative structures of layout to the MOSFETs implementations, regarding both planar and three-dimensional CMOS technologies of nanometric scale transistors implementation.The Diamond and OCTO layout styles are alternatives, in this context, to improve the MOSFETs performance and, therefore, the performance of analogic and digital integrated circuits, without any additional cost to the currently settled process of CMOS fabrication of integrated circuits.Initially, the Diamond layout style for MOSFET was specially conceived and patented in Brazil, by a simply change in the layout, in which the geometric form of the gate was changed from rectangular to hexagonal, in order to use the Corner Effect (CE) on the longitudinal direction of the MOSFET channel, called Longitudinal Corner Effect (LCE), to enhance the resultant longitudinal electric field along the channel, and consequently, the average drift velocity of the mobile carriers in the channel, the drain current, the transconductance, the transconductance over drain current ratio and the Early Voltage, and to reduce the on-state source-drain series resistance, depending on the ± angle of the hexagonal region of the gate, focusing the analogic IC applications, since the channel length of these devices are always longer than the minimum dimension allowed by the CMOS fabrication process.Results from three-dimensional numerical simulations and experimental data show great improvements from the Diamond layout style when applied to planar MOSFETs, compared to the conventional counterpart, regarding the same gate area, geometric factor and bias condition.The OCTO layout style applied to MOSFET is an evolution from the Diamond proposal and was specially designed to improve the breakdown voltage and to strengthen its robustness regarding electro-static discharges (ESD) effects. It presents an octogonal gate geometry, resulting in three electrical field components, in contrast with the only two components in the Diamond structure, that gives an even higher resultant longitudinal electrical field than in the Diamond one. Results from three-dimensional numerical simulations and from experimental data prove that the OCTO layout style for MOSFETs also can significantly improve the performance of the transistors, when we compare to the equivalent conventional ones, regarding the same gate area and bias condition.Therefore, the proposed work has the objective of applying these innovative and promising Diamond and OCTO layout styles on three-dimensional MOSFETs, called FinFETs, and to perform a comparative study of the analogic and digital main parameters between the Diamond and OCTO FinFETs and the conventional counterparts, in order to verify the possible advantages and disadvantages from these new layout styles.Another extremely important objective of this work is to convince the researchers from research centers and the national and international semiconductors and integrated circuits industry experts, which own the CMOS fabrication process of three-dimensional MOSFETs (like IMEC from Belgium, from instance, through the cooperation with Prof. Dr. Cor Clayes), the possibility of being manufactured on nanometric scale FinFET with a high technology.