Advanced search
Start date

Evaluation of Electrical Performance of SOI Nanowire Transistors for Low Power Applications

Grant number: 21/02993-3
Support Opportunities:Scholarships in Brazil - Scientific Initiation
Effective date (Start): June 01, 2021
Effective date (End): May 31, 2022
Field of knowledge:Engineering - Electrical Engineering - Electrical Materials
Principal Investigator:Michelly de Souza
Grantee:Vinícius Rodrigues Prates
Host Institution: Centro Universitário FEI (UNIFEI). Campus de São Bernardo do Campo. São Bernardo do Campo , SP, Brazil


Currently, most electronic circuits use field effect transistors built according to Metal-Oxide-Semiconductor (MOSFET) technology. Scaling semiconductor devices consists of reducing the dimensions of MOS transistors and interconnections in integrated circuits (ICs), allowing for higher density of integration, higher speed and lower power consumption. From an economic point of view, the reduction of the devices allows to obtain improved performance with lower cost per function. From an electrical point of view, devices dimensions reduction allows for better performance and reduction of the supply voltage, contributing to minimize the dynamic power. Therefore, it becomes possible to include several applications in a single product, such as smartphones, with low energy consumption, ensuring good battery life. The technology of manufacturing ICs in silicon on insulator (SOI) wafers has been constituted as an important alternative to replace conventional MOS technology, in the fabrication of ICs in ultra large scale of integration, aiming at the continuous reduction of dimensions. In this technology, devices are fabricated in a thin layer of silicon, separated from the rest of the substrate by an insulator. MOS transistors in this technology provide improvements such as reduced junction capacitances and larger carrier mobility, minimizing, or delaying for more complex technological generations, the occurrence of undesirable parasitic effects, resulting from the reduction of dimensions.For transistors with extremely small dimensions, in the order of 22 nm, multiple gate transistors are a promising alternative to solve the problems resulting from the continuous reduction of MOS transistors transistors, improving the electrostatic control of the charges in channel region, which reduces the occurrence of short channel effects. This way, multiple gate transistors, such as FinFETs, have gained attention from the scientific community due to their good electrical performance. More recently, the reduction in the height of the Si fin in FinFET-type structures has given rise to the nanowires MOS transistors which, due to their cross-section of few nanometers, allow excellent electrostatic control, and make possible to obtain transistors with a channel length of a few nanometers.In addition to the several advantages presented by SOI transistors for different applications, the adoption of the SOI wafer also allows the integration of sensors and circuits in the same area of silicon. For example, one can mention lateral PIN diodes that, when reversely biased, allow the obtaining of photodetectors for low wavelengths, with high quantum efficiency and low values of dark current, resulting in low power in an off state. Semiconductor diodes can also be used as temperature sensors, with high linearity over a wide operating range.Thus, advanced semiconductor devices implemented in SOI technology in a fully depleted Si layer constitute a very attractive option for IoT (Internet of Things) applications, which require high performance, low power voltage, low power consumption, good reliability, in addition to flexibility in design solutions, not only at the level of circuit architecture, but also at the level of device technology.In this Scientific Initiation project, a study on the electrical operation of nanometer transistor SOI nanowires will be carried out, aiming at low power consumption applications. The study will be carried out through electrical measurements, in addition to 3D numerical simulations, in order to verify the analog performance of these transistors with the reduction of supply voltages, including the subthreshold operation. Nanowire MOS transistors manufactured in CEA-Leti, France will be used.

News published in Agência FAPESP Newsletter about the scholarship:
Articles published in other media outlets (0 total):
More itemsLess items

Please report errors in scientific publications list using this form.