Developing an ArchC behavioral model for the AVR32 instruction set architecture

• Grant number: 13/15890-1
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: December 01, 2013
• End date: November 30, 2014
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Alexandro José Baldassin
• Grantee: Bruno Chinelato Honorio
• Host Institution: Instituto de Geociências e Ciências Exatas (IGCE). Universidade Estadual Paulista (UNESP). Campus de Rio Claro. Rio Claro , SP, Brazil
• Associated research grant: 11/19373-6 - Understanding and exploiting energy/performance tradeoffs in concurrent algorithms, AP.JP

Abstract

Architecture Description Languages (ADL) have been employed in processor modeling due to their high abstraction level and ease of design space exploration. One of the most popular ADLs is ArchC, developed by the Institute of Computing, UNICAMP. ArchC allows, starting from a processor description, the automatic generation of simulators and a set of binary tools, such as compiler backends and assemblers. In this project we seek to build a behavioral model for the AVR32 instruction set architecture. Among other features, the architecture allows 16-bit compact instructions and is widely employed in embedded systems.