Support for execution of automatically generated processors in FPGA

• Grant number: 17/04018-2
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: May 01, 2017
• End date: April 30, 2018
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Rodolfo Jardim de Azevedo
• Grantee: Lucas de Camargo Barros de Castro
• Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil

Abstract

Over the past few years, multi-core processors have been gaining more presence in the market allowing a great diversity of homogeneous architectures. Despite the possibility of having multiple cores working together, they are normally identical or have 2 variations (big.LITTLE), leaving few micro-architectural alternatives (pipeline size, number of execution units, etc) to the project designer, until recently a tool, named FabScalar, was developed to make the exploration of different micro-architectures easier, since it enables the creation of more than 30.000 core configurations. This tool is being even more flexibilized through the Ph.D work of Priscila Aparecida de Moraes Ioris, entitled "Automação na síntese de processadores", which seeks to create a methodology and tooling capable of generating processors with different microarchitectures and with different ISA to flexibilize the execution of applications. During the experimentation and evaluation phase, it is desirable that these new processors could be implemented in FPGA (Field Programmable Gate Array), programmable and highly efficient electronic device. Under these circumstances, this project proposes to study and to create the set of mechanisms called Board Support Package (BSP), responsible for allowing the processor generated by this new tool to be implemented in FPGA and also garanting it is communicable with other devices, such as memory and peripherals, respecting the generality and efficiency it requires. (AU)