Dual dispach superscalar RISC-V for FPGAs.

• Grant number: 24/01738-8
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date until: June 01, 2024
• End date until: May 31, 2025
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Ricardo Menotti
• Grantee: Lucas Arruk Mendes
• Host Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos , SP, Brazil

Abstract

A new era of processors is being led by RISC-V, an open standard architecture free of royalties, which allows the development of more flexible and less costly implementations. This scenario raises the present project, which aims to propose a superscalar RISC-V processor with dual-issue static scheduling for execution on FPGA devices, specified in Verilog HDL. The starting point of the work will be a detailed investigation of consolidated implementations of RISC-V processors found in the literature. A first version of the processor will be generated, seeking to combine ideas that add the advantages of each investigated proposal and eliminate their respective disadvantages. Building upon the first version of the processor, it will be refined through an iterative procedure consisting of three steps: i) integrity verification (review of correct functionality) and performance tests using specific benchmarks aimed at a multi-objective analysis; ii) production of solutions for overall performance improvement; and iii) implementation of these solutions. Finally, with the definition of a processor through established concepts, the execution of a Real-Time Operating System (RTOS) will be performed for a more robust validation.