Designing a task-centric manycore architecture

• Grant number: 17/02682-2
• Support Opportunities: Scholarships in Brazil - Master
• Start date: July 01, 2017
• End date: July 02, 2019
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Agreement: Coordination of Improvement of Higher Education Personnel (CAPES)
• Principal Investigator: Alfredo Goldman vel Lejbman
• Grantee: Lucas Henrique Morais
• Host Institution: Instituto de Matemática e Estatística (IME). Universidade de São Paulo (USP). São Paulo , SP, Brazil
• Associated scholarship(s): 18/00687-0 - Adding native support for task scheduling to a RISC-V multi-core processor, BE.EP.MS

Abstract

Along the last decade, the ubiquity of multi-core systems from cell phones to desktops have made the development of good parallelization techniques an issue of paramount importance. In this context, Task Parallelism rises as a relevant parallel programming paradigm, enabling the parallelization of applications from several domains without demanding too much programming effort. In fact, based only on programmer-provided annotations, Task Parallelism aims to enable the execution of imperative programs in a dataflow manner, analogously to how instruction level parallelism (ILP) works in superscalar architectures under the Tomasulo algorithm.On the other hand, since Task Parallelism relies on the on-line inference of task dependences, the performance of task parallel applications is highly dependent on how fast the runtime can infer such dependences. In order to improve runtime performance, R&D groups in LG (USA), MagiCore (Finland), Technion (Israel), TU Berlin and the Barcelona Supercomputing Center (BSC) have proposed HW accelerators for speeding up dependence inference. Unfortunately such approaches have been severely impaired by the use of high-latency, low-bandwidth communication mechanisms for connecting the accelerator to the rest of the system. By leveraging in the experience acquired from a previous UNICAMP-LG project, this proposal aims to overcome such limitations by defining and implementing a novel processor architecture where (1) tightly integrated hardware support for task scheduling and (2) processor instructions specifically designed for performing task-scheduling activities eliminate most of the communication overhead between the runtime and the dependence resolution HW-acceleration engine, considerably improving the applicability of the Task Parallelism paradigm. (AU)

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

MORAIS, LUCAS; SILVA, VITOR; GOLDMAN, ALFREDO; ALVAREZ, CARLOS; BOSCH, JAUME; FRANK, MICHAEL; ARAUJO, GUIDO; ASSOC COMP MACHINERY. Adding Tightly-Integrated Task Scheduling Acceleration to a RISC-V Multi-core Processor. MICRO'52: THE 52ND ANNUAL IEEE/ACM INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, v. N/A, p. 12-pg., 2019-01-01. (17/02682-2, 14/25694-8, 18/00687-0)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

MORAIS, Lucas Henrique. Adding native support for task scheduling to a Linux-capable RISC-V multicore system. 2019. Master's Dissertation - Universidade de São Paulo (USP). Instituto de Matemática e Estatística (IME/SBI) São Paulo.