An Architecture for FPGA Acceleration of Stochastic Programming Algorithms

• Grant number: 17/15236-0
• Support Opportunities: Scholarships in Brazil - Doctorate
• Start date: August 01, 2017
• End date: September 30, 2021
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Guido Costa Souza de Araújo
• Grantee: Catalina Munoz Morales
• Host Institution: Instituto de Computação (IC). Universidade Estadual de Campinas (UNICAMP). Campinas , SP, Brazil
• Associated research grant: 13/08293-7 - CCES - Center for Computational Engineering and Sciences, AP.CEPID

Abstract

Diverse disciplines including Physics, Chemistry, Biology, Medicine, and Engineering deal with decision dilemmas described as optimization problems with multiple variables and constraints. Such problems seek to minimize cost, time or resource and can be governed by requirements or constraints that involve variables with levels of uncertainty, which generate optimization problems known as Stochastic Problems. Stochastic Programming comprises a series of methods developed to solve optimization problems that can only be probabilistically described. To obtaining an optimum solution on reasonable processing time and precision, such methods require a great amount of computing resources. With the aim to answer to such processing requirements, novel computer architectures have been developed over the last years. Parallel processing architectures based on GPU and FPGA accelerators have been proposed in order to increase system performance. However, both FPGA and GPU accelerator devices, as well as traditional processing units (CPUs), present particular capabilities and operating constraints that require a careful analysis if an efficient architecture is desired. The present research proposal seeks to exploit parallel heterogeneous architectures with FPGA accelerators that enable the implementation of efficient algorithms targeting the solution stochastic optimization problems.

Scientific publications

(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)

MORALES, CATALINA MUNOZ; MURARI, RAFAEL; DE CARVALHO, JOAO P. L.; HONORIO, BRUNO CHINELATO; BALDASSIN, ALEXANDRO; ARAUJO, GUIDO; SOUSA, L; ROMA, N; TOMAS, P. Accelerating Graph Applications Using Phased Transactional Memory. EURO-PAR 2021: PARALLEL PROCESSING, v. 12820, p. 14-pg., 2021-01-01. (17/15236-0)

MORALES, CATALINA MUNOZ; HONORIO, BRUNO; BALDASSIN, ALEXANDRO; ARAUJO, GUIDO; IEEE COMP SOC. Improving Phased Transactional Memory via Commit Throughput and Capacity Estimation. 2021 IEEE 33RD INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND HIGH PERFORMANCE COMPUTING (SBAC-PAD 2021), v. N/A, p. 10-pg., 2021-01-01. (17/15236-0)

Academic Publications

(References retrieved automatically from State of São Paulo Research Institutions)

MORALES, Catalina Munoz. Melhorando a transição de modo em implementações de memória transacional em fases. 2022. Doctoral Thesis - Universidade Estadual de Campinas (UNICAMP). Instituto de Computação Campinas, SP.