Dynamic Function Exchange in FPGAs to redefine multicore architectures at runtime.

• Grant number: 23/15719-2
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: March 01, 2024
• End date: February 28, 2025
• Field of knowledge: Physical Sciences and Mathematics - Computer Science
• Principal Investigator: Vanderlei Bonato
• Grantee: Téo Sobrino Alves
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil

Abstract

The usage of multicore systems is quite prevalent in the context of data processing, given the trends toward parallelism. Such systems possess static and homogeneous architectures. The incorporation of dynamic reconfiguration of Field-Programmable Gate Arrays (FPGAs) in multicore systems enables a dynamic and heterogeneous architecture, thereby enhancing the system's flexibility and adaptability during runtime. Implementing dynamic reconfiguration is a challenging endeavor as it introduces complexities into the system and imposes limitations.The primary objective of this study is to investigate the use of dynamic reconfiguration in multicore systems with the aim of achieving performance improvements, despite the additional complexity and limitations. To accomplish this, techniques will be employed to develop a reconfigurable processor derived from a conventional multicore processor. It is expected that a runtime-adaptable system can be created, surpassing the performance of the base processor while maintaining a similar quantity of logical resources.