Development of a Many-Core Processor Simulator with Network on Chip Network Architecture using an Interactive Teaching Approach

• Grant number: 23/17497-7
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: March 01, 2024
• End date: February 28, 2025
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Emerson Carlos Pedrino
• Grantee: Breno Dias Arantes dos Santos
• Host Institution: Centro de Ciências Exatas e de Tecnologia (CCET). Universidade Federal de São Carlos (UFSCAR). São Carlos , SP, Brazil

Abstract

In the literature, several Many-Core acceleration simulators and Network-on-Chip networks are described, which in turn have a high complexity of use by undergraduate students, as they use low-level hardware concepts, which requires a high degree of knowledge announced in high-performance computer architecture in general, thus generating a very deep learning curve and making their use for teaching purposes unfeasible, especially for students who are in the initial series of the Computer Engineering course. Therefore, in this Scientific Initiation (IC) project, we intend to design and implement a simplified simulator using the Python language, abstracting structural concepts from the Network-on-Chip (NOCs) architecture, such as grid size, performance and efficiency (latency, energy, fault tolerance, etc.), to analyze its effectiveness, which contributes to the study and evaluation of different mapping algorithms and routing techniques most used in this scenario.