UVM based verification applied to readout ASIC for micropattern gaseous detectors

• Grant number: 24/06703-8
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: August 01, 2024
• End date: July 31, 2025
• Field of knowledge: Engineering - Electrical Engineering - Electrical, Magnetic and Electronic Circuits
• Principal Investigator: Bruno Cavalcante de Souza Sanches
• Grantee: Nicolas Abgar Tavares Guimarães
• Host Institution: Escola Politécnica (EP). Universidade de São Paulo (USP). São Paulo , SP, Brazil
• Associated research grant: 20/04867-2 - High energy physics and instrumentation with the LHC-CERN, AP.ESP

Abstract

This project aims to develop a verification environment using the System Verilog language and the UVM methodology for the SALSA chip, an integrated circuit for readout and data processing of signals incoming from gaseous detectors, mainly those used in the field of particle physics. This integrated circuit brings the innovation of high configurability in the analog parameters, making it possible to be used in micropattern gaseous detectors, wire chambers and photomultipliers. Furthermore, the proposed ASIC already has intended use in the Brookhaven National Laboratory (United States). Concerning the proposal of new technology, it is necessary to verify the chip to guarantee the intended functionality and avoid the production of malfunctioning prototypes. However, taking into account that the integrated circuit is being developed with new circuits that did not exist previously in the market, there is no intellectual property available for testing, thus having the need to develop a new verification environment with proprietary code and methods. Therefore, it is important to develop a modern verification environment adopting System Verilog and the UVM methodology, both of which are highly used in the market today and also allow the verification to be reusable and modular, fitting perfectly into the process of prototyping this chip in an iterative way.