Advanced search
Start date
Betweenand

Design of a signal adquisition and digital processing ASIC for time projection chamber of ALICE experiment

Abstract

ALICE (A Large Ion Collider Experiment) is one of four major experiments of particle accelerator LHC (Large Hadron Collider) installed in the European laboratory CERN. The management committee of the LHC accelerator has just approved a program update for this experiment. Among the upgrades planned for the coming years of the ALICE experiment is to improve the resolution and tracking efficiency maintaining the excellent particles identification ability, and to increase the read-out event rate to 100KHz. In order to achieve this, it is necessary to update the Time Projection Chamber detector (TPC) and Muon tracking (MCH) detector modifying the read-out electronic. The TPC detector is the main device of the central barrel of the ALICE experiment for tracking and identification of charged particles. The TPC requires migrating from MWPC (Multi Wire Proportional Chamber) to GEM (Gas Electron Multiplier) to achieve the read-out rate required. The current read out-unit is not suitable for this migration due to two reasons. First, the signal pre- amplification integrated circuit (named PASA) of the read-out unit does not support signals with positive polarity, which is not adequate for signals generated by GEM detectors. The second limitation is related to the scheme used for data reading. The integrated circuit of analog-digital conversion and digital processing does not support continuous readout: TPC signals sampling and data storage on memory cannot happen simultaneously. Furthermore, these integrated circuits dissipate excessive power (considering the high number of channels required).This project proposes the design, simulation, fabrication, experimental testing and validation of a signal acquisition and digital processing prototype ASIC that can be used for signals detection in the TPC and MCH, which supports negative polarity, with 32 channels per chip, continuous data readout with lower power consumption than the previous versions. (AU)

Articles published in Pesquisa FAPESP Magazine about the research grant:
Chip for particle collisions 
Sopa primordial 
Primordial soup 
Sopa primordial 
Articles published in Agência FAPESP Newsletter about the research grant:
Articles published in other media outlets (0 total):
More itemsLess items
VEICULO: TITULO (DATA)
VEICULO: TITULO (DATA)

Scientific publications (8)
(References retrieved automatically from Web of Science and SciELO through information on FAPESP grants and their corresponding numbers as mentioned in the publications by the authors)
SANCHES, B.; BREGANT, M.; HERNANDEZ, H.; VAN NOIJE, W.. Successive approximation register ADC single event effects protection and evaluation. Journal of Instrumentation, v. 17, n. 4, p. 8-pg., . (14/12664-3, 13/06885-4)
ADOLFSSON, J.; AYALA PABON, A.; BREGANT, M.; BRITTON, C.; BRULIN, G.; CARVALHO, D.; CHAMBERT, V.; CHINELLATO, D.; ESPAGNON, B.; HERNANDEZ HERRERA, H. D.; et al. SAMPA Chip: the New 32 Channels ASIC for the ALICE TPC and MCH Upgrades. Journal of Instrumentation, v. 12, . (12/04583-8, 14/12664-3, 13/06885-4)
HERNANDEZ, HUGO; DE SOUZA SANCHES, BRUNO CAVALCANTE; CARVALHO, DIONISIO; BREGANT, MARCO; PABON, ARMANDO AYALA; DA SILVA, RONALDO WILTON; HERNANDEZ, RAUL ACOSTA; WEBER, TIAGO OLIVEIRA; DO COUTO, ANDRE LUIS; CAMPOS, ARTHUR; et al. A Monolithic 32-Channel Front End and DSP ASIC for Gaseous Detectors. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, v. 69, n. 6, 1, p. 2686-2697, . (13/06885-4, 14/12664-3)
SANCHES, BRUNO; VAN NOIJE, WILHELMUS. An Optimized Radiation Tolerant Baseline Correction Filter for HEP Using AI Methodologies. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, v. 68, n. 5, p. 1789-1799, . (14/12664-3, 13/06885-4)
SANCHES, BRUNO; VAN NOIJE, WILHELMUS; IEEE. A Radiation Tolerant Baseline Correction Filter for Front-ends in High Energy Physics Experiments. 2020 IEEE 11TH LATIN AMERICAN SYMPOSIUM ON CIRCUITS & SYSTEMS (LASCAS), v. N/A, p. 4-pg., . (13/06885-4, 14/12664-3)
HERNANDEZ, HUGO; DE SOUZA SANCHES, BRUNO CAVALCANTE; CARVALHO, DIONISIO; BREGANT, MARCO; PABON, ARMANDO AYALA; DA SILVA, RONALDO WILTON; HERNANDEZ, RAUL ACOSTA; WEBER, TIAGO OLIVEIRA; DO COUTO, ANDRE LUIS; CAMPOS, ARTHUR; et al. A Monolithic 32-Channel Front End and DSP ASIC for Gaseous Detectors. IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, v. 69, n. 6, p. 12-pg., . (14/12664-3, 13/06885-4)
DE CARVALHO, DIONISIO; SANCHES, BRUNO; DE CARVALHO, M.; VAN NOIJE, WILHELMUS; IEEE. A flexible stand-alone FPGA-based ATE for ASIC manufacturing tests. 2018 IEEE 19TH LATIN-AMERICAN TEST SYMPOSIUM (LATS), v. N/A, p. 6-pg., . (14/12664-3, 13/06885-4)
HERNANDEZ, HUGO; CARVALHO, DIONISIO; SANCHES, BRUNO; SEVERO, LUCAS C.; VAN NOIJE, WILHELMUS; IEEE. Current Mode 1.2-Gbps SLVS Transceiver for Readout Front-end ASIC. 2017 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), v. N/A, p. 4-pg., . (14/12664-3, 13/06885-4)

Please report errors in scientific publications list using this form.