ChipCflow - Implementation of the Iteractive Operators

• Grant number: 10/09090-4
• Support Opportunities: Scholarships in Brazil - Scientific Initiation
• Start date: August 01, 2010
• End date: July 31, 2011
• Field of knowledge: Physical Sciences and Mathematics - Computer Science - Computer Systems
• Principal Investigator: Jorge Luiz e Silva
• Grantee: Isabela Rodrigues do Prado Rossales
• Host Institution: Instituto de Ciências Matemáticas e de Computação (ICMC). Universidade de São Paulo (USP). São Carlos , SP, Brazil

Abstract

Different from traditional processors, Moore´s Law was one of the reasons to duplicate cores, and at least until today it is the solution for safe consumption and operation of systems using millions of transistors. In terms of software, parallelism will be a tendency over the coming years. One of the challenges is to create tools for programmers who use HLL (High Level Language) producing hardware directly. These tools should use the utmost experience of the programmers and the flexibility of FPGA (Field Programmable Gate Array). The main aspect of the existing tools which directly convert HLL into hardware is dependence graphics. On the other hand, a dynamic dataflow architecture has implicit parallelism. ChipCflow is a tool to convert C directly into hardware that uses FPGA as a partial reconfiguration based on a dynamic dataflow architecture. In this project, the iterative operator, that will be used to control data partner with the same tagged-token will be implemented.