Full text
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| Author(s): |
Bruno Chinelato Honorio
Total Authors: 1
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| Document type: | Doctoral Thesis |
| Press: | Campinas, SP. |
| Institution: | Universidade Estadual de Campinas (UNICAMP). Instituto de Computação |
| Defense date: | 2023-02-01 |
| Examining board members: |
Guido Costa Souza de Araújo;
Márcio Bastos Castro;
André Rauber Du Bois;
Marcio Machado Pereira;
Luiz Eduardo Busato
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| Advisor: | Guido Costa Souza de Araújo |
| Abstract | |
With chip manufacturers such as Intel, IBM and ARM offering native support for trans- actional memory in their instruction set architectures, memory transactions are getting increasingly popular in the industry and as a research topic. Despite this recent increase in popularity on the hardware side of transactional memory (HTM), software support for transactional memory (STM) is still scarce and the only compiler with transactional support currently available, the GNU Compiler Collection (GCC), does not generate code that achieves desirable performance and it is not easy to use, making the programmer have to take into account how functions are used and annotate them appropriately, which is far from the ideal abstraction of TM. Modern approaches seek to combine both HTM and STM to better exploit performance. In particular, Phased TMs (PhTMs) systems execute transactions in phases, not allowing both hardware and software transactions to run concurrently to avoid coordination over- heads. One of its main issues is designing a good transition mode heuristics that exploits HTM as much as possible considering the STM side problems of performance. This Thesis makes 3 main contributions to transactional memory research: Firstly, it proposes a novel annotation mechanism (TMFree) that selectively eliminates unnecessary transactional memory read/write barriers from compiler generated code. It does that by annotating variables that do not need to be instrumented with a type qualifier. Using the type qualifier, speedups of up to 7x and a reduction by 95% in barriers were shown. Secondly, it proposes a language-level construct (TMFree) that eases programmability of compiler-generated transactional code. In this case, TMFree work as a C style casting on functions that do not need to be instrumented. This work automates a lot of what the programmer had to do manually, significantly decreasing the job the programmer has to do. Results show that the programmer only has to manually insert 5 of this TMFree casting to make the applications work with no performance loss, compared to the 358 annotations that were necessary for the same results. And finally, it proposes a transition mode mechanism (CTM) to better exploit both modes of phases transactional memory. It does that by using a different approach in PhTM: the use of commit throughput and cache simulation to mimic the behavior of HTM storage constraints while in STM mode. Experimental results have shown that up to 5x of speedups were achieved when using this new approach. This thesis, then, makes a case for transactional memory being a strong contender for parallel programming techniques, with many of the results presented being the state-of- the-art for transactional memory research (AU) | |
| FAPESP's process: | 19/04536-9 - Improving performance of collision cross section calculation through component annotation |
| Grantee: | Bruno Chinelato Honorio |
| Support Opportunities: | Scholarships in Brazil - Doctorate |