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Author(s)

Carlos Eduardo Viana

• Document type: Doctoral Thesis
• Press: São Paulo.
• Institution: Universidade de São Paulo (USP). Escola Politécnica (EP/BC)
• Defense date: 2002-09-06

Examining board members

Nilton Itiro Morimoto; Olivier André Paul Bonnaud; Joan Ramon Morante Lleonart; Tayeb Mohammed brahim; Jacobus Willibrordus Swart

• Advisor: Nilton Itiro Morimoto

Abstract

The objective of this Ph.D. work is the development of a CMOS thin film transistors (TFT\'s) fabrication process at low temperature. Initially, we studied the silicon oxide thin films deposition process by PECVD and HD-PECVD with TEOS, aiming its application as TFT\'s gate insulator. We studied the reactions of TEOS molecules with oxygen in the presence or not of argon. Different analysis techniques were applied to characterize the deposited silicon oxide layers: Optical Emission Spectroscopy, Ellipsometry, Fourier Transform Infra-Red Spectroscopy, Atomic Force Microscopy and µ-RAMAN. MOS capacitors were fabricated and the best results obtained with the PECVD silicon oxide deposited films (as gate insulator) were: leakage current density: \"JLK = 2.3 x 10´POT.-6´ A/cm² @ 4 MV/cm\", breakdown strength: \"EBD = 9.4 MV/cm\" and effective density charge: \"QSS = 7.3 x 10´POT.11´ cm­²\". The electrical properties of the PECVD silicon oxide layers were not good enough to be applied as TFT\'s gate insulator. Hence, a new reaction chamber was built. In this chamber, the plasma is inductively coupled, what improves the plasma density in the silicon oxide deposition process - HD-PECVD. The HD-PECVD/TEOS silicon oxide layers showed the following electrical results: \"JLK = 2.8 x 10´POT.-5´ A/cm² @ 4 MV/cm\", \"EBD = 10.6 MV/cm\" and \"QSS = 2.0 x 10´POT.12´ cm-²\". The second part of this work shows the developed TFT\'s fabrication process at low temperature (600°C), with undoped and in-situ dopedpolycrystalline silicon deposited by LPCVD. ) The solid phase crystallization process was used. The electrical properties of the P and N types TFT\'s were: electric field effect mobility: \"µP = 15 cm²/V.s\", \"µN = 63 cm²/V.s\", sub-threshold slope: \"SP = 1 V/dec\", \"SN = 1 V/dec\" and threshold voltage: \"VTP = -9 V\" and \"VTN = 4 V\". The pMOS and nMOS inverters worked with suitable characteristics. The results showed the compatibility between the fabrication process of both P and N types TFT\'s over the same glass substrate. A photolithographic set of masks, to manufacture the CMOS-like TFT\'s, was designed based on the obtained results. The results for the P type TFT, obtained in the CMOS-like TFT\'s fabrication process were: µP = 55 cm²/V.s, SP = 1.2 V/dec, VTP = -19 V. For the N type TFT: µN = 55 cm²/V.s, SN = 1.5 V/dec, VTN = -14 V. The CMOS-like TFT\'s inverters presented the following results: maximum power supply \"VDD = 20 V\"; transition voltage \"VIT = 6.3 V\", transition slope \"S = 191 V/dec\" and output voltage: \"VOUT = 19.99 V\" for input voltage of: \"VIN = 0 V\". TFT\'s were also fabricated using the HD-PECVD/TEOS silicon oxide as gate dielectric. The obtained electrical characteristics were: for the P type (VTP = -7.9V, µP = 14 cm²/V.s, SP = -0.9 V/dec, (ION/IOFF)P = 1.7 x 10´POT.6´) and for the N type (VTN = 1.2V, µN = 28 cm²/V.s, SN = 1 V/dec, (ION/IOFF)N = 5 x 10´POT.7´). These results show the feasibility to fabricate TFT\'s using the HD-PECVD/TEOS siliconoxide as gate dielectric. (AU)