Untitled in english

Author(s)

Jefferson Perez Rodrigues Costa

• Document type: Master's Dissertation
• Press: São Paulo.
• Institution: Universidade de São Paulo (USP). Escola Politécnica (EP/BC)
• Defense date: 2000-11-06

Examining board members

Jose Vieira do Vale Neto; Douglas Casagrande; Wang Jiang Chau

• Advisor: Jose Vieira do Vale Neto

Abstract

Allocation is the High Level Synthesis task that reaches a data path definition obeying hardware restriction and optimizing the chip area and performance. Testability is a sequence of procedures that ensures that an ASIC is working correctly. Self-Testability is the case where the whole test procedure is implemented in the chip. A design is said full testable when, in the test mode, all the possible faults can be detected. This dissertation presents a method to consider the testability of the ASIC during the allocation process. A few other than the usual hardware restrictions are imposed to ensures the self-testability. The achieved data path will be self-testable and will have the smallest possible area. Usually, this kind of optimization problem is NP-Complete. In our case, heuristics are used to reach a good solution in an acceptable computing time. This work shows the heuristics used in our allocation algorithm and a case of study, that validates the whole process, is shown, also. (AU)